公开(公告)号：US10310743B2

公开(公告)日：2019-06-04

申请号：US15714743

申请日：2017-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Parthasarathy Gajapathy

IPC: G06F1/12 ,  G06F3/06

Abstract: A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.

公开(公告)号：US20230393929A1

公开(公告)日：2023-12-07

申请号：US17829576

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

公开(公告)号：US20190244654A1

公开(公告)日：2019-08-08

申请号：US16388716

申请日：2019-04-18

Applicant: Micron Technology, Inc

Inventor： Parthasarathy Gajapathy

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C8/06 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C8/06 ,  G11C8/16 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4093

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

公开(公告)号：US10373672B2

公开(公告)日：2019-08-06

申请号：US16039995

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G11C11/4093 ,  G11C8/16

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

公开(公告)号：US20190095105A1

公开(公告)日：2019-03-28

申请号：US15714743

申请日：2017-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Parthasarathy Gajapathy

IPC: G06F3/06

Abstract: A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.

公开(公告)号：US20130070509A1

公开(公告)日：2013-03-21

申请号：US13672018

申请日：2012-11-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Parthasarathy Gajapathy

IPC: G11C5/06

CPC classification number: G11C7/1075 ,  G11C11/4096 ,  G11C11/4097

Abstract: Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus.

公开(公告)号：US12019512B2

公开(公告)日：2024-06-25

申请号：US17829576

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

公开(公告)号：US11545209B2

公开(公告)日：2023-01-03

申请号：US17333203

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  Kallol Mazumder

IPC: G11C11/4076 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/4093

Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

公开(公告)号：US11003240B2

公开(公告)日：2021-05-11

申请号：US16684183

申请日：2019-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C11/408 ,  G06F3/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

公开(公告)号：US10481676B2

公开(公告)日：2019-11-19

申请号：US16205356

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C7/10 ,  G06F3/00 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.