公开(公告)号：US20240354195A1

公开(公告)日：2024-10-24

申请号：US18649721

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F11/14 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/1441 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/3037 ,  G06F11/3055 ,  G06F11/3058 ,  G06F2201/805

Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication

公开(公告)号：US20230367718A1

公开(公告)日：2023-11-16

申请号：US17663255

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

公开(公告)号：US11809311B2

公开(公告)日：2023-11-07

申请号：US17397393

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Christian M. Gyllenskog ,  Jonathan Scott Parry ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0629 ,  G06F12/0253 ,  G06F12/0292

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

公开(公告)号：US11568953B2

公开(公告)日：2023-01-31

申请号：US17152352

申请日：2021-01-19

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G11C29/48 ,  G06F13/16

Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer selecting between a respective slave PHY and the master bus; a plurality of electrical circuits, wherein each electrical circuit of the plurality of electrical circuits is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.

公开(公告)号：US11520525B2

公开(公告)日：2022-12-06

申请号：US17315015

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

公开(公告)号：US20220357884A1

公开(公告)日：2022-11-10

申请号：US17315015

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

公开(公告)号：US11226894B2

公开(公告)日：2022-01-18

申请号：US16230313

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Christian M. Gyllenskog ,  Jonathan Scott Parry ,  Stephen Hanna

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

公开(公告)号：US20210109666A1

公开(公告)日：2021-04-15

申请号：US17129087

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20210020259A1

公开(公告)日：2021-01-21

申请号：US16514685

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G11C29/48 ,  G06F13/16

Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer controlled by the test mode signal selecting between a respective slave PHY and the master bus; a plurality of memory components, wherein each memory component of the plurality of memory components is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.

公开(公告)号：US20200210080A1

公开(公告)日：2020-07-02

申请号：US16237134

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.