公开(公告)号：US10607690B2

公开(公告)日：2020-03-31

申请号：US16557688

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US10607687B2

公开(公告)日：2020-03-31

申请号：US15857327

申请日：2017-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US10418093B1

公开(公告)日：2019-09-17

申请号：US16118798

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/08 ,  G11C11/408

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US11232829B2

公开(公告)日：2022-01-25

申请号：US16814863

申请日：2020-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US11222975B2

公开(公告)日：2022-01-11

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20200075083A1

公开(公告)日：2020-03-05

申请号：US16557688

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C11/4091 ,  G11C7/08 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US20190206480A1

公开(公告)日：2019-07-04

申请号：US15857327

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108

CPC classification number: G11C11/4091 ,  H01L27/10897

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.