公开(公告)号：US20210028308A1

公开(公告)日：2021-01-28

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20190279984A1

公开(公告)日：2019-09-12

申请号：US16418150

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4094 ,  G11C5/02 ,  H01L29/08 ,  G11C11/408 ,  G11C11/403

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US10347635B2

公开(公告)日：2019-07-09

申请号：US15986628

申请日：2018-05-22

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/408 ,  H01L49/02 ,  G11C11/4097 ,  H01L29/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4091

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US11222975B2

公开(公告)日：2022-01-11

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20200075083A1

公开(公告)日：2020-03-05

申请号：US16557688

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C11/4091 ,  G11C7/08 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US10607690B2

公开(公告)日：2020-03-31

申请号：US16557688

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US10418093B1

公开(公告)日：2019-09-17

申请号：US16118798

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steve V. Cole ,  Benjamin A. Millemon ,  Toby D. Robbs ,  J. W. Thompson

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/08 ,  G11C11/408

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

公开(公告)号：US20190006365A1

公开(公告)日：2019-01-03

申请号：US15986628

申请日：2018-05-22

Applicant: Micron Technology , Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L29/08 ,  H01L49/02

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US20220131003A1

公开(公告)日：2022-04-28

申请号：US17568133

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US10930653B2

公开(公告)日：2021-02-23

申请号：US16418150

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/408 ,  H01L49/02 ,  G11C11/4097 ,  H01L29/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4091

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.