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公开(公告)号：US20220075601A1
公开(公告)日：2022-03-10
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
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Patent Agency Ranking
公开(公告)号：US12106070B2
公开(公告)日：2024-10-01
申请号：US17375024
申请日：2021-07-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Lee , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F7/5443 , G06J1/00 , Y02D10/00
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating, the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.
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公开(公告)号：US11966628B2
公开(公告)日：2024-04-23
申请号：US17830471
申请日：2022-06-02
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wei-Chen Wang , Han-Wen Hu , Yung-Chun Li , Huai-Mu Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
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公开(公告)号：US11914887B2
公开(公告)日：2024-02-27
申请号：US17403927
申请日：2021-08-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Han-Wen Hu , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G06F12/0246
Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
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公开(公告)号：US11526328B2
公开(公告)日：2022-12-13
申请号：US16781868
申请日：2020-02-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hung-Sheng Chang , Han-Wen Hu , Hsiang-Pang Li , Tzu-Hsien Yang , I-Ching Tseng , Hsiang-Yun Cheng , Chia-Lin Yang
Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
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公开(公告)号：US20210240443A1
公开(公告)日：2021-08-05
申请号：US16781868
申请日：2020-02-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hung-Sheng Chang , Han-Wen Hu , Hsiang-Pang Li , Tzu-Hsien Yang , I-Ching Tseng , Hsiang-Yun Cheng , Chia-Lin Yang
Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
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