-
公开(公告)号：US12106070B2
公开(公告)日：2024-10-01
申请号：US17375024
申请日：2021-07-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Lee , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F7/5443 , G06J1/00 , Y02D10/00
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating, the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.
-
公开(公告)号：US11914887B2
公开(公告)日：2024-02-27
申请号：US17403927
申请日：2021-08-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Han-Wen Hu , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G06F12/0246
Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
-
公开(公告)号：US11656988B2
公开(公告)日：2023-05-23
申请号：US17542557
申请日：2021-12-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang
IPC: G06F12/00 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/1024
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.
-
Patent Agency Ranking
公开(公告)号：US20220075601A1
公开(公告)日：2022-03-10
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
-
公开(公告)号：US11809838B2
公开(公告)日：2023-11-07
申请号：US17365034
申请日：2021-07-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Lee , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F7/5443 , G11C7/06
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.
-
公开(公告)号：US12169702B2
公开(公告)日：2024-12-17
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
-
公开(公告)号：US11704246B2
公开(公告)日：2023-07-18
申请号：US17539257
申请日：2021-12-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Bo-Rong Lin , Ming-Liang Wei , Hsiang-Pang Li , Nai-Jia Dong , Hsiang-Yun Cheng , Chia-Lin Yang
IPC: G06F12/0804
CPC classification number: G06F12/0804 , G06F2212/601
Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.
-
公开(公告)号：US20230161556A1
公开(公告)日：2023-05-25
申请号：US17701725
申请日：2022-03-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang , Wei-Chen Wang
IPC: G06F7/544 , G06F7/527 , G06F7/72 , G06F12/0882 , G06F13/16
CPC classification number: G06F7/5443 , G06F7/5272 , G06F7/729 , G06F12/0882 , G06F13/1673
Abstract: A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.017 seconds)
