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公开(公告)号：US11848046B2
公开(公告)日：2023-12-19
申请号：US17694771
申请日：2022-03-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu
IPC: G11C16/16 , G11C11/4091 , G11C11/4096 , G11C11/4074 , G11C11/4099
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4096 , G11C11/4099
Abstract: The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.
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公开(公告)号：US12169702B2
公开(公告)日：2024-12-17
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
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公开(公告)号：US20230161556A1
公开(公告)日：2023-05-25
申请号：US17701725
申请日：2022-03-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang , Wei-Chen Wang
IPC: G06F7/544 , G06F7/527 , G06F7/72 , G06F12/0882 , G06F13/16
CPC classification number: G06F7/5443 , G06F7/5272 , G06F7/729 , G06F12/0882 , G06F13/1673
Abstract: A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.
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公开(公告)号：US20220076762A1
公开(公告)日：2022-03-10
申请号：US17321933
申请日：2021-05-17
Applicant: Macronix International Co., Ltd.
Inventor： Yung-Chun Lee , Yu-Ming Huang , Han-Wen Hu
Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.
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公开(公告)号：US11809838B2
公开(公告)日：2023-11-07
申请号：US17365034
申请日：2021-07-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Lee , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F7/5443 , G11C7/06
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.
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Patent Agency Ranking
公开(公告)号：US11664058B1
公开(公告)日：2023-05-30
申请号：US17564340
申请日：2021-12-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li
IPC: G11C7/14 , G11C7/10 , H03K19/017 , G11C7/12 , G11C8/08
CPC classification number: G11C7/14 , G11C7/1039 , G11C7/1063 , G11C7/12 , G11C8/08 , H03K19/01742
Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.
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公开(公告)号：US11354123B2
公开(公告)日：2022-06-07
申请号：US17026347
申请日：2020-09-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Han-Wen Hu , Yueh-Han Wu , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.
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公开(公告)号：US11119674B2
公开(公告)日：2021-09-14
申请号：US16279494
申请日：2019-02-19
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Han-Wen Hu
Abstract: A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.
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公开(公告)号：US11656988B2
公开(公告)日：2023-05-23
申请号：US17542557
申请日：2021-12-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang
IPC: G06F12/00 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/1024
Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.
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公开(公告)号：US11631467B2
公开(公告)日：2023-04-18
申请号：US17321933
申请日：2021-05-17
Applicant: Macronix International Co., Ltd.
Inventor： Yung-Chun Lee , Yu-Ming Huang , Han-Wen Hu
Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.
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