公开(公告)号：US20250107080A1

公开(公告)日：2025-03-27

申请号：US18472229

申请日：2023-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Mao-Yuan Weng ,  Ting-Feng Liao ,  Kuang-Wen Liu

IPC: H10B43/27

Abstract: A method of fabricating a memory device at least includes the following steps. A first stack structure is formed above a substrate. The first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers alternately stacked. A top layer of the first stack structure includes a plurality of anti-oxidation atoms therein. A second stack structure is formed on the first stack structure. The second stack structure includes a plurality of second insulating layers and a plurality of middle layers alternately stacked. A slit trench is formed to extend from the second stack structure to a top first conductor layer of the plurality of first conductor layers. A protective layer is formed on a sidewall of the top first conductive layer exposed by the slit trench. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20250098162A1

公开(公告)日：2025-03-20

申请号：US18466820

申请日：2023-09-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Ting-Feng Liao ,  Mao-Yuan Weng ,  Kuang-Wen Liu

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes, from bottom to top, a substrate, a laminated layer and a stacked structure. Vertical channel pillars penetrate through the stacked structure and the laminated layer. First isolation structures are disposed aside the vertical channel pillars and penetrate through a lower part of the stacked structure. Second isolation structures are disposed over the first isolation structures and penetrate through an upper part of the stacked structure. Common source lines are disposed aside the vertical channel pillars and penetrate through the stacked structure and part of the laminated layer. From a top view, the common source lines extend in a first direction. Each of the first and second isolation structures has, in the first direction, two wide end portions respectively adjacent to two common source lines. The memory device may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US11374099B2

公开(公告)日：2022-06-28

申请号：US16930505

申请日：2020-07-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ting-Feng Liao ,  Sheng-Hong Chen ,  Kuang-Wen Liu

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11582

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

公开(公告)号：US20190157289A1

公开(公告)日：2019-05-23

申请号：US15818972

申请日：2017-11-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ting-Feng Liao

IPC: H01L27/11582 ,  H01L29/06 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/532 ,  H01L29/10 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor structure includes a plurality of sub-array structures separated from each other by a plurality of isolation structures. The semiconductor structure further includes a three-dimensional array of memory cells. The memory cells include a plurality of cell groups disposed in the sub-array structures, respectively. The semiconductor structure further includes a plurality of conductive structures. Each of the conductive structures includes a plurality of conductive columns correspondingly disposed in each of the isolation structures along an extending direction of the isolation structures. The conductive columns penetrate through the each of the isolation structures. Each of the conductive columns has a circular cross section.

公开(公告)号：US20180294273A1

公开(公告)日：2018-10-11

申请号：US15481676

申请日：2017-04-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ting-Feng Liao ,  Yi-Chen Wang

IPC: H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G11C16/04

CPC classification number: H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53295

Abstract: A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate. The insulating layers are disposed on the first conductive layer. The second conductive layers are alternatively stacked with the insulating layers and insulated from the first conductive layer. The contact plug passes through the insulating layers and the second conductive layers, insulates from the second conductive layers and electrically contacts to the first conductive layer. The dummy plug, corresponds to the at least one contact plug, passes through the insulating layers and the second conductive layers, and insulates from the second conductive layers and the first conductive layer.

公开(公告)号：US20180261621A1

公开(公告)日：2018-09-13

申请号：US15455185

申请日：2017-03-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Hong Chen ,  Ting-Feng Liao

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11582

Abstract: A semiconductor structure includes a substrate and a plurality of sub-array structures disposed on the substrate. The sub-array structures separated from each other by a plurality of trenches. The semiconductor structure includes a three-dimensional array of memory cells. The memory cells include a plurality of cell groups disposed in the sub-array structures, respectively. The semiconductor structure further includes a plurality of support pillars and a plurality of conductive pillars disposed in the trenches. The support pillars and the conductive pillars in each of the trenches are alternately arranged in an extending direction of the trenches. The semiconductor structure further includes a plurality of conductive lines disposed in the trenches and on the support pillars and the conductive pillars. Each of the conductive lines connects the conductive pillars thereunder.