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公开(公告)号：US10446573B2
公开(公告)日：2019-10-15
申请号：US15818972
申请日：2017-11-21
发明人： Ting-Feng Liao
IPC分类号： H01L27/11 , H01L27/11582 , H01L29/06 , H01L27/11556 , H01L23/528 , H01L23/532 , H01L29/10 , H01L21/768 , H01L21/762 , H01L27/11565 , H01L27/11519
摘要： A semiconductor structure includes a plurality of sub-array structures separated from each other by a plurality of isolation structures. The semiconductor structure further includes a three-dimensional array of memory cells. The memory cells include a plurality of cell groups disposed in the sub-array structures, respectively. The semiconductor structure further includes a plurality of conductive structures. Each of the conductive structures includes a plurality of conductive columns correspondingly disposed in each of the isolation structures along an extending direction of the isolation structures. The conductive columns penetrate through the each of the isolation structures. Each of the conductive columns has a circular cross section.
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公开(公告)号：US09431406B1
公开(公告)日：2016-08-30
申请号：US14724573
申请日：2015-05-28
发明人： Ting-Feng Liao , Yao-Fu Chan
IPC分类号： H01L27/115 , H01L21/265 , H01L21/266 , H01L21/02 , H01L29/66 , H01L21/308 , H01L21/28
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/266 , H01L21/28273 , H01L29/42324 , H01L29/4983 , H01L29/6656 , H01L29/66825
摘要： A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively on the stacked structures are formed on a substrate. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening which exposes a portion of top surfaces of the hard mask patterns and a portion of the substrate between the stacked structures. The exposed portion of the substrate is removed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a trench in the substrate. An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench.
摘要翻译： 提供半导体器件及其形成方法。 在基板上形成分别在堆叠结构上的至少两个分离的堆叠结构和至少两个硬掩模图案。 在基板上形成图案化的掩模层。 图案化掩模层具有暴露硬掩模图案的顶表面的一部分和在堆叠结构之间的衬底的一部分的开口。 通过使用图案化掩模层和硬掩模图案作为掩模来去除衬底的暴露部分，以便在衬底中形成沟槽。 通过使用图案化掩模层和硬掩模图案作为掩模来执行离子注入工艺，以在沟槽周围的衬底中形成掺杂区域。
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公开(公告)号：US11991882B2
公开(公告)日：2024-05-21
申请号：US17528068
申请日：2021-11-16
IPC分类号： H10B43/27 , H01L21/02 , H01L21/28 , H01L21/311 , H01L21/768 , H01L23/48 , H01L29/51
CPC分类号： H10B43/27 , H01L21/02532 , H01L21/02636 , H01L21/31111 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L23/481 , H01L29/40117 , H01L29/513 , H01L29/518
摘要： A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.
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公开(公告)号：US20220077187A1
公开(公告)日：2022-03-10
申请号：US17528068
申请日：2021-11-16
IPC分类号： H01L27/11582 , H01L23/48 , H01L29/51 , H01L21/02 , H01L21/768 , H01L21/28 , H01L21/311
摘要： A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.
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公开(公告)号：US20200020711A1
公开(公告)日：2020-01-16
申请号：US16035421
申请日：2018-07-13
发明人： Ting-Feng Liao
IPC分类号： H01L27/11582 , H01L29/10 , H01L27/11565 , H01L21/311 , H01L21/28 , H01L21/02 , H01L21/768
摘要： A memory device and a method of fabricating the same are provided. The memory device includes a substrate, a first circuit structure, a plurality of first conductive pillars, a second circuit structure, and a plurality of second conductive pillars. The first circuit structure is disposed on the substrate. The first conductive pillars are disposed in the first circuit structure and arranged along a first direction. The first conductive pillars are extended from an upper layer of the first circuit structure to the substrate. The second circuit structure is disposed on the first circuit structure. The second conductive pillars are disposed in the second circuit structure and arranged along the first direction. The second conductive pillars are extended from an upper layer of the second circuit structure to the first circuit structure. Each of the second conductive pillars is electrically connected to each of the first conductive pillars respectively.
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公开(公告)号：US10170492B2
公开(公告)日：2019-01-01
申请号：US15481676
申请日：2017-04-07
发明人： Ting-Feng Liao , Yi-Chen Wang
IPC分类号： H01L27/115 , H01L27/11556 , H01L23/522 , H01L23/528 , H01L23/532 , G11C16/04
摘要： A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate. The insulating layers are disposed on the first conductive layer. The second conductive layers are alternatively stacked with the insulating layers and insulated from the first conductive layer. The contact plug passes through the insulating layers and the second conductive layers, insulates from the second conductive layers and electrically contacts to the first conductive layer. The dummy plug, corresponds to the at least one contact plug, passes through the insulating layers and the second conductive layers, and insulates from the second conductive layers and the first conductive layer.
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公开(公告)号：US11917828B2
公开(公告)日：2024-02-27
申请号：US17314528
申请日：2021-05-07
发明人： Ting-Feng Liao , Mao-Yuan Weng , Kuang-Wen Liu
IPC分类号： H10B41/00 , H10B43/50 , H01L23/522 , H01L21/768 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
CPC分类号： H10B43/50 , H01L21/76877 , H01L23/5226 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
摘要： Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.
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公开(公告)号：US11211401B2
公开(公告)日：2021-12-28
申请号：US16728394
申请日：2019-12-27
IPC分类号： H01L27/115 , H01L27/11582 , H01L23/48 , H01L29/51 , H01L21/02 , H01L21/768 , H01L21/28 , H01L21/311
摘要： A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.
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公开(公告)号：US20210202518A1
公开(公告)日：2021-07-01
申请号：US16728394
申请日：2019-12-27
IPC分类号： H01L27/11582 , H01L23/48 , H01L29/51 , H01L21/02 , H01L21/311 , H01L21/28 , H01L21/768
摘要： A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.
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公开(公告)号：US10050051B1
公开(公告)日：2018-08-14
申请号：US15465770
申请日：2017-03-22
发明人： Ting-Feng Liao , I-Ting Lin
IPC分类号： H01L29/49 , H01L27/11568
摘要： A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.
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