公开(公告)号：US11302366B2

公开(公告)日：2022-04-12

申请号：US17070340

申请日：2020-10-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Su-Chueh Lo ,  Yung-Feng Lin

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/445 ,  G06F9/38

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

公开(公告)号：US10297316B2

公开(公告)日：2019-05-21

申请号：US15687687

申请日：2017-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Yun-Chen Chou ,  Hsin-Yi Ho

IPC: G11C13/00

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

公开(公告)号：US09412425B2

公开(公告)日：2016-08-09

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

公开(公告)号：US09170601B2

公开(公告)日：2015-10-27

申请号：US13888430

申请日：2013-05-07

Applicant: Macronix International Co., Ltd.

Inventor： Yung-Feng Lin

IPC: G06F1/04 ,  G06F13/16

CPC classification number: G06F1/04 ,  G06F13/161

Abstract: A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.

Abstract translation: 解码电路包括预触发信号生成单元，比较单元和起始信号生成单元。 预触发信号产生单元接收先前的编码数据，并且当接收到的命令的前一编码数据与预定命令的对应的先前编码数据匹配时，产生预触发信号。 当所接收的命令的后一编码数据与预定命令的后一个编码数据相同时，比较单元产生匹配信号。 启动信号生成单元根据预触发信号和匹配信号输出起始信号。 启动信号开始相应的预定命令的操作。

公开(公告)号：US20150206557A1

公开(公告)日：2015-07-23

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US09001604B2

公开(公告)日：2015-04-07

申请号：US13801500

申请日：2013-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US20140269125A1

公开(公告)日：2014-09-18

申请号：US13801500

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US20130246836A1

公开(公告)日：2013-09-19

申请号：US13888430

申请日：2013-05-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F13/161

Abstract: A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.

Abstract translation: 解码电路包括预触发信号生成单元，比较单元和起始信号生成单元。 预触发信号产生单元接收先前的编码数据，并且当接收到的命令的前一编码数据与预定命令的对应的先前编码数据匹配时，产生预触发信号。 当所接收的命令的后一编码数据与预定命令的后一个编码数据相同时，比较单元产生匹配信号。 启动信号生成单元根据预触发信号和匹配信号输出起始信号。 启动信号开始相应的预定命令的操作。