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35 条记录 (耗时 0.022 秒)

    Display apparatus with flat display panel
    13.
    发明授权
    Display apparatus with flat display panel 失效
    具有平板显示面板的显示装置

    公开(公告)号：US06624798B1

    公开(公告)日：2003-09-23

    申请号：US08816684

    申请日：1997-03-13

    申请人： Masami Aoki ,  Toyoshi Kawada ,  Haruo Koizumi

    发明人： Masami Aoki ,  Toyoshi Kawada ,  Haruo Koizumi

    IPC分类号： G09G328

    CPC分类号： G09G3/296 ,  G09G3/2932 ,  G09G2310/0218 ,  G09G2310/066 ,  G09G2330/023

    摘要： A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver successively supplies scanning pulses to the scanning electrodes with scanning timing, and an address driver supplies address pulses according to display data to the address electrodes in synchronism with the scanning timing. The address electrodes include first and second address electrodes disposed adjacent to each other. The address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.

    摘要翻译： 等离子体显示面板显示装置包括具有多个寻址电极的平面显示面板和横向于寻址电极延伸的多个扫描电极，并且与地址电极相对地设置，其间限定有放电空间。 扫描电极驱动器以扫描定时向扫描电极依次提供扫描脉冲，并且地址驱动器根据显示数据向寻址电极提供与扫描定时同步的寻址脉冲。 寻址电极包括彼此相邻布置的第一和第二寻址电极。 施加到第一寻址电极的地址脉冲上升，并且施加到第二寻址电极的寻址脉冲以其间的预定时间差落下。

    Automatic gain control method and automatic gain control circuit
    16.
    发明授权
    Automatic gain control method and automatic gain control circuit 失效
    自动增益控制方式和自动增益控制电路

    公开(公告)号：US06965656B2

    公开(公告)日：2005-11-15

    申请号：US10073417

    申请日：2002-02-13

    申请人： Haruo Koizumi

    发明人： Haruo Koizumi

    IPC分类号： H03G3/20 ,  H03G3/30 ,  H04B1/16 ,  H04B1/26 ,  H04L27/38 ,  H04L27/08 ,  H04B7/00

    CPC分类号： H04L27/3809

    摘要： A demodulator controls gains of an RF-AGC amplifier and an IF-AGC amplifier so as to maintain an input level to the demodulator constant. In this case, the demodulator estimates a signal level of an RF input based on the sum of the gains directed to the both AGC amplifiers, and changes methods for distributing a gain to the AGC amplifiers, according to whether or not the signal level exceeds a predetermined Take Over Point. Further, a first detection and smoothing circuit detects an output level of the RF-AGC amplifier, and a second detection and smoothing circuit detects an output of a mixer. Besides, a comparison circuit controls the gain of the RF-AGC amplifier so that a difference between the output levels comes to be a predetermined value. With this structure, an automatic gain control circuit which can achieve high receiving sensitivity and low waveform distortion simultaneously can be realized even when manufacturing dispersion is caused.

    摘要翻译： 解调器控制RF-AGC放大器和IF-AGC放大器的增益，以保持解调器的输入电平恒定。 在这种情况下，解调器基于针对两个AGC放大器的增益的总和来估计RF输入的信号电平，并且根据信号电平是否超过 预定接管点。 此外，第一检测和平滑电路检测RF-AGC放大器的输出电平，第二检测和平滑电路检测混频器的输出。 此外，比较电路控制RF-AGC放大器的增益，使得输出电平之间的差成为预定值。 利用这种结构，即使在产生分散时也能够实现同时实现高接收灵敏度和低波形失真的自动增益控制电路。

    Non-volatile semiconductor memory device having EEPROM cell, dummy cell, and sense circuit for increasing reliability and enabling one-bit operation
    17.
    发明授权
    Non-volatile semiconductor memory device having EEPROM cell, dummy cell, and sense circuit for increasing reliability and enabling one-bit operation 失效
    具有EEPROM单元，虚设单元和检测电路的非易失性半导体存储器件，用于增加可靠性并实现一位操作

    公开(公告)号：US5303197A

    公开(公告)日：1994-04-12

    申请号：US690482

    申请日：1991-04-24

    申请人： Takumi Miyashita ,  Toshiyuki Teramoto ,  Haruo Koizumi

    发明人： Takumi Miyashita ,  Toshiyuki Teramoto ,  Haruo Koizumi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/28

    摘要： A non-volatile semiconductor memory device comprises an EEPROM cell, a dummy cell, and a sense circuit. The EEPROM cell, the dummy cell and the sense circuit are operatively connected to a drain column line and a control column line, and the sense circuit reads out the content written in the EEPROM cell by the difference between a current flowing through the EEPROM cell from the drain column line and a current flowing through the dummy cell from the control column line. Consequently, write/erase operations of data for each one bit can be carried out in one operation, and access time can be shortened and deterioration of a cell transistor can be decreased in a read-out operation.

    摘要翻译： 非易失性半导体存储器件包括EEPROM单元，虚设单元和感测电路。 EEPROM单元，虚拟单元和感测电路可操作地连接到排列列线和控制列线，并且感测电路通过流过EEPROM单元的电流之间的差读出EEPROM单元中写入的内容 漏极列线和从控制柱线流过虚拟电池的电流。 因此，可以在一个操作中执行每一位的数据的写入/擦除操作，并且可以缩短访问时间，并且在读出操作中可以减小单元晶体管的劣化。

    Method of diagnosing integrated logic circuit
    18.
    发明授权
    Method of diagnosing integrated logic circuit 失效
    诊断集成逻辑电路的方法

    公开(公告)号：US4996659A

    公开(公告)日：1991-02-26

    申请号：US84153

    申请日：1987-08-12

    申请人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    发明人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    IPC分类号： G01R31/305 ,  G01R31/3193

    CPC分类号： G01R31/3193 ,  G01R31/305

    摘要： A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.

    摘要翻译： 一种诊断具有功能块的集成逻辑电路的方法，其中测试信号被提供给逻辑电路; 通过使用诸如电子束探测装置或激光束探测装置的非接触探测装置来检测来自至少一个功能块的输入信号和输出信号; 利用检测到的输入信号对功能块的正常逻辑运算进行仿真，以提供模拟输出信号; 检测和模拟的输出信号相互比较; 并且根据比较的结果将功能块确定为正常或异常。 当功能块包括多个逻辑元件时，通过非接触探测装置检测功能元件的输出，将检测到的输出与对应的模拟输出进行比较并重复检测，可以将异常的原因追溯到故障功能元件 并比较功能块中的其他功能元素，直到比较结果重合。 将作为比较结果提供一致的信号的功能元件确定为故障功能元件。

    Wrapping box
    20.
    外观设计
    Wrapping box 失效
    包装盒

    公开(公告)号：USD497799S1

    公开(公告)日：2004-11-02

    申请号：US29176684

    申请日：2003-02-24

    申请人： Haruo Koizumi

    设计人： Haruo Koizumi