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    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip
    4.
    发明授权
    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip 失效
    集成在半导体芯片上的单片半导体集成电路器件和微计算机

    公开(公告)号：US5784637A

    公开(公告)日：1998-07-21

    申请号：US414157

    申请日：1995-03-31

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

    摘要翻译： 形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线 或输入/输出端口）和可变逻辑电路（或子处理器）。 可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。 可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。 存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

    Single-chip microcomputer
    5.
    发明授权
    Single-chip microcomputer 失效
    单片机

    公开(公告)号：US5428808A

    公开(公告)日：1995-06-27

    申请号：US217826

    申请日：1994-03-25

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

    摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

    Method of diagnosing integrated logic circuit
    6.
    发明授权
    Method of diagnosing integrated logic circuit 失效
    诊断集成逻辑电路的方法

    公开(公告)号：US4996659A

    公开(公告)日：1991-02-26

    申请号：US84153

    申请日：1987-08-12

    申请人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    发明人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    IPC分类号： G01R31/305 ,  G01R31/3193

    CPC分类号： G01R31/3193 ,  G01R31/305

    摘要： A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.

    摘要翻译： 一种诊断具有功能块的集成逻辑电路的方法，其中测试信号被提供给逻辑电路; 通过使用诸如电子束探测装置或激光束探测装置的非接触探测装置来检测来自至少一个功能块的输入信号和输出信号; 利用检测到的输入信号对功能块的正常逻辑运算进行仿真，以提供模拟输出信号; 检测和模拟的输出信号相互比较; 并且根据比较的结果将功能块确定为正常或异常。 当功能块包括多个逻辑元件时，通过非接触探测装置检测功能元件的输出，将检测到的输出与对应的模拟输出进行比较并重复检测，可以将异常的原因追溯到故障功能元件 并比较功能块中的其他功能元素，直到比较结果重合。 将作为比较结果提供一致的信号的功能元件确定为故障功能元件。

    Single chip microprocessor for satisfying requirement specification of users
    7.
    发明授权
    Single chip microprocessor for satisfying requirement specification of users 失效
    单芯片微处理器，用于满足用户的要求规格

    公开(公告)号：US5426744A

    公开(公告)日：1995-06-20

    申请号：US203761

    申请日：1994-03-01

    申请人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    发明人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    IPC分类号： G06F9/24 ,  G06F9/38 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

    CPC分类号： G06F9/3879 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867 ,  G06F9/24 ,  G06F9/3897

    摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

    摘要翻译： 本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。 形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。 结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。 可以通过任意形成的逻辑功能来满足各种用户的需求规格。

    Microcomputer having a PROM including data security and test circuitry
    8.
    发明授权
    Microcomputer having a PROM including data security and test circuitry 失效
    具有PROM的微型计算机，包括数据安全和测试电路

    公开(公告)号：US5175840A

    公开(公告)日：1992-12-29

    申请号：US726113

    申请日：1991-06-21

    申请人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

    发明人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1433

    摘要： Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate or body. The second inhibition means is coupled to the data bus and provides a second inhibiting operation to prevent access operations to the memory from outside the semiconductor body via the data bus and permanently disables the access operations to the memory irrespective of a releasing or termination of the first inhibiting operation after the second inhibiting operation has taken effect.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）的易测试性和数据安全性可以通过设置焊盘和输入/输出（I / O）电路来实现，该电路提供半导体衬底上的EEPROM测试所需的地址，数据和控制信号， 通过在基板上布置由EEPROM器件组成的两级测试I / O截取电路，使得一旦完成测试，由于具有内置的数据安全功能，防止了对半导体衬底之外的非法存取。 具有这种能力的微型计算机设置有用于处理数据的中央处理单元（CPU），诸如EEPROM的存储器，其通过公共总线（其传送数据，地址和控制信号）与CPU进行内部通信，其他 比在测试模式期间以及提供安全性的第一和第二抑制电路。 第一禁止电路耦合到数据总线，并提供第一禁止操作以防止对存储器的访问操作。 第一抑制电路根据来自半导体衬底或主体外部的信号来释放第一禁止操作。 第二禁止装置耦合到数据总线，并且提供第二禁止操作，以防止经由数据总线从半导体主体外部对存储器的访问操作，并且永久地禁用对存储器的访问操作，而不管第一 第二禁止操作之后的禁止操作已经起作用。

    Semiconductor integrated circuit having CPU and multiplier
    9.
    发明授权
    Semiconductor integrated circuit having CPU and multiplier 失效
    具有CPU和乘法器的半导体集成电路

    公开(公告)号：US5832248A

    公开(公告)日：1998-11-03

    申请号：US555262

    申请日：1995-11-08

    申请人： Kazumasa Kishi ,  Shigeki Masumura ,  Hideo Nakamura ,  Kouki Noguchi ,  Shumpei Kawasaki ,  Yasushi Akao

    发明人： Kazumasa Kishi ,  Shigeki Masumura ,  Hideo Nakamura ,  Kouki Noguchi ,  Shumpei Kawasaki ,  Yasushi Akao

    IPC分类号： G06F7/52 ,  G06F7/506 ,  G06F7/523 ,  G06F9/302 ,  G06F9/32 ,  G06F9/38 ,  G06F15/78 ,  G06F12/00

    CPC分类号： G06F9/3001 ,  G06F15/7864 ,  G06F9/325 ,  G06F9/3885

    摘要： A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.

    摘要翻译： 逻辑LSI芯片包括CPU，总线，存储器和乘法器。 此外，逻辑LSI芯片包括用于在从存储器读出数据的同时从CPU向乘法器传送关于与读出的数据相关的乘法指令的命令的命令信号线，使得乘法器 从总线直接获取数据。 因此，当CPU从存储器读取数据时，与读出的数据相关的乘法指令的命令从CPU传送到乘法器。 当乘法器执行重复操作时，总线周期控制电路接收来自乘法器的状态信号，并且总线周期控制电路通过发信号通知CPU来延迟向乘法器发出后续命令来响应状态信号。

    Microinstruction controlled data processor
    10.
    发明授权
    Microinstruction controlled data processor 失效
    微指令控制数据处理器

    公开(公告)号：US4494195A

    公开(公告)日：1985-01-15

    申请号：US444711

    申请日：1982-11-26

    申请人： Kouki Noguchi ,  Takashi Tsunehiro ,  Hideo Nakamura

    发明人： Kouki Noguchi ,  Takashi Tsunehiro ,  Hideo Nakamura

    IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

    CPC分类号： G06F9/267

    摘要： Herein disclosed is a microinstruction controlled data processor in which a microinstruction memory (i.e., an ROM) is driven in each predetermined cycle thereby to generate a plurality of microinstructions in accordance with a page address it receives and in which a general microinstruction contains the page address and the displacement address of the plural preceding microinstructions. One of the plural instructions read out of the ROM is selected upon each read-out operation. The page and displacement addresses in the microinstruction thus selected are set in an address register at the timings for reading out the plural microinstructions. Moreover, a displacement address generator for selecting the plural microinstructions read out of the ROM generates the displacement addresses which are different in dependence upon whether a branch instruction exists in the instructions selected during the same number of cycles as that of the plurality or not and whether the branching operation succeeds or not in case the branch instruction exists.

    摘要翻译： 这里公开了一种微指令控制数据处理器，其中在每个预定周期中驱动微指令存储器（即，ROM），从而根据其接收的页地址生成多个微指令，并且其中一般微指令包含页面地址 以及多个前面的微指令的位移地址。 在每次读出操作时选择从ROM读出的多个指令之一。 如此选择的微指令中的页面和位移地址在用于读出多个微指令的定时处被设置在地址寄存器中。 此外，用于选择从ROM中读出的多个微指令的位移地址发生器产生根据在与多个循环相同的周期期间选择的指令中是否存在分支指令而不同的位移地址，以及是否 在分支指令存在的情况下，分支操作成功或不成功。