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    Semiconductor device having T-shaped gate structure comprising in situ sidewall spacers and method of forming the semiconductor device
    14.
    发明授权
    Semiconductor device having T-shaped gate structure comprising in situ sidewall spacers and method of forming the semiconductor device 失效
    具有包括原位侧壁间隔件的T形门结构的半导体器件和形成半导体器件的方法

    公开(公告)号：US07148145B2

    公开(公告)日：2006-12-12

    申请号：US10400598

    申请日：2003-03-27

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L21/302

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28114

    摘要： Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.

    摘要翻译： 形成多晶硅线，具有延伸超过限定所需CD的下部的上部。 因此，可以在多晶硅线路的上部形成尺寸增加的金属硅化物层，使得所得到的栅极结构表现出非常低的最终薄层电阻。 此外，在形成多晶硅生产线的过程中实现原位侧壁间隔物，并且没有额外的步骤和/或成本。

    Method of removing features using an improved removal process in the fabrication of a semiconductor device
    15.
    发明授权
    Method of removing features using an improved removal process in the fabrication of a semiconductor device 失效
    使用改进的去除工艺在半导体器件的制造中去除特征的方法

    公开(公告)号：US07041583B2

    公开(公告)日：2006-05-09

    申请号：US10624776

    申请日：2003-07-22

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L21/3205 ,  H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/7833

    摘要： A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer and/or a disposable sidewall spacer which are to be removed in a subsequent etch removal process. The bottom anti-reflective coating layer and/or the disposable sidewall spacer are irradiated by heavy inert ions to alter the structure of the irradiated features and to increase concurrently the etch rate of the employed materials, for example, silicon nitride or silicon reacted nitride.

    摘要翻译： 公开了一种在制造半导体器件中改善一次性特征的蚀刻行为的方法。 半导体器件包括底部抗反射涂层和/或一次性侧壁间隔物，其将在随后的蚀刻去除过程中被去除。 底部抗反射涂层和/或一次性侧壁间隔物被重的惰性离子照射以改变被照射特征的结构，并同时增加所用材料的蚀刻速率，例如氮化硅或硅反应的氮化物。

    Semiconductor device having a retrograde dopant profile in a channel region
    16.
    发明申请
    Semiconductor device having a retrograde dopant profile in a channel region 有权
    半导体器件在沟道区域具有逆向掺杂物分布

    公开(公告)号：US20050151202A1

    公开(公告)日：2005-07-14

    申请号：US11072142

    申请日：2005-03-04

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

    摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

    摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

    Sidewall spacer based fet alignment technology
    17.
    发明授权
    Sidewall spacer based fet alignment technology 有权

    公开(公告)号：US06593197B2

    公开(公告)日：2003-07-15

    申请号：US09811733

    申请日：2001-03-19

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659

    摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

    Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same
    19.
    发明授权
    Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
    具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法

    公开(公告)号：US06306698B1

    公开(公告)日：2001-10-23

    申请号：US09558963

    申请日：2000-04-25

    申请人： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66507

    摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).

    摘要翻译： 本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。 在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109） 位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。 在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及 图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。 该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。 该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

    Method of forming low resistance metal silicide region on a gate electrode of a transistor
    20.
    发明授权
    Method of forming low resistance metal silicide region on a gate electrode of a transistor 有权
    在晶体管的栅电极上形成低电阻金属硅化物区域的方法

    公开(公告)号：US06423634B1

    公开(公告)日：2002-07-23

    申请号：US09557697

    申请日：2000-04-25

    申请人： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

    IPC分类号： H01L2144

    CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/66545

    摘要： In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.

    摘要翻译： 在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。 保护层防止在栅电极上同时形成金属硅化物区域。 此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。 接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。 然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。