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26 条记录 (耗时 0.027 秒)

    Reconfigurable SIMD vector processing system
    11.
    发明申请
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US20080104164A1

    公开(公告)日：2008-05-01

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Instruction and logic for a simon block cipher
    12.
    发明授权
    Instruction and logic for a simon block cipher 有权
    一个simon块密码的指令和逻辑

    公开(公告)号：US09473296B2

    公开(公告)日：2016-10-18

    申请号：US14227718

    申请日：2014-03-27

    申请人： Sanu K. Mathew ,  Himanshu Kaul ,  Mark A. Anders

    发明人： Sanu K. Mathew ,  Himanshu Kaul ,  Mark A. Anders

    IPC分类号： H04L9/06 ,  G06F21/62 ,  G09C1/00

    CPC分类号： H04L9/0618 ,  G06F21/62 ,  G09C1/00 ,  H04L2209/24

    摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.

    摘要翻译： 处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。 数据变换电路包括移位数据存储寄存器的内容的逻辑。 密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。 常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。 存储单元的数量小于常量列表的大小。

    Encoder and decoder circuits for dynamic bus
    14.
    发明申请
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US20050146357A1

    公开(公告)日：2005-07-07

    申请号：US10744084

    申请日：2003-12-24

    申请人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

    Method of creating a demographic based personalized pronunciation dictionary
    15.
    发明申请
    Method of creating a demographic based personalized pronunciation dictionary 审中-公开

    公开(公告)号：US20200372110A1

    公开(公告)日：2020-11-26

    申请号：US16419028

    申请日：2019-05-22

    申请人： Himanshu Kaul

    发明人： Himanshu Kaul

    IPC分类号： G06F17/27 ,  G10L15/02 ,  G10L15/28

    摘要： The present invention is related to the method of creating a demographic based personalized pronunciation dictionary for a user wherein the method comprising: determining at least one demographic information of the user, receiving at least one voice input from the user in association with the at least one demographic information, determining at least one voice characteristics in association with the at least one voice input received from the user in association with the at least one demographic information, determining at least one non-demographic information, identifying at least one pronunciation information from a demographic specific pronunciation dictionary located in a database in association with the at least one non-demographic information, determining, upon receiving at least one voice input from the user in association with at least one non-demographic information, at least one voice characteristics in association with the at least one voice input received from the user in association with the at least one non-demographic information, creating a personalized pronunciation dictionary for the user and storing the personalized pronunciation dictionary for the user in the database.

    Transition-aware signaling
    16.
    发明授权
    Transition-aware signaling 失效
    过渡感知信令

    公开(公告)号：US06870402B2

    公开(公告)日：2005-03-22

    申请号：US10389320

    申请日：2003-03-14

    申请人： Dennis M. Sylvester ,  Himanshu Kaul

    发明人： Dennis M. Sylvester ,  Himanshu Kaul

    IPC分类号： H03K3/3565 ,  H03K5/08 ,  H03K5/1534 ,  H03K5/22 ,  H04L25/02

    CPC分类号： H04L25/0292 ,  H03K3/3565 ,  H03K5/084 ,  H03K5/088 ,  H03K5/1534

    摘要： An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a transition signal in response to a detection of a transition from a first state to a second state on the interconnect line and further generates the transition signal in response to a detection of a transition from the second state to the first state on said interconnect line. The receiver further includes an output signal control circuit that, in response to the transition signal, selectively outputs either a present state of said interconnect line or a next state of the interconnect line stored in the receiver.

    摘要翻译： 公开了一种用于集成芯片上的改进的接收机电路。 接收器电路插入在集成电路中的电气部件之间的互连线中。 接收器电路具有转换检测电路，其响应于在互连线上从第一状态到第二状态的转变的检测而产生转换信号，并且响应于检测到来自第二状态的转变而产生转换信号 状态到所述互连线上的第一状态。 接收机还包括输出信号控制电路，响应于转换信号，选择性地输出所述互连线的当前状态或存储在接收机中的互连线的下一状态。

    Method of registering and identifying a user of a voice-controlled device
    17.
    发明申请
    Method of registering and identifying a user of a voice-controlled device 有权

    公开(公告)号：US20210012129A1

    公开(公告)日：2021-01-14

    申请号：US16508320

    申请日：2019-07-11

    申请人： Himanshu Kaul

    发明人： Himanshu Kaul

    IPC分类号： G06K9/00 ,  G10L17/22

    摘要： The present invention is related to a method of registering and identifying a user of a voice-controlled device. The method comprising: registering the user of the device, determining at least one of a facial, eye and body features of the user upon determining at least one characteristic of a voice input from the user is below a threshold level, determining an output upon comparing the determined at least one of the facial, eye and body features of the user with a prestored information associated with the user in a database and identifying the user in accordance with the determined output.

    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT
    18.
    发明申请
    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
    紧凑型低功耗高级加密标准电路

    公开(公告)号：US20150086007A1

    公开(公告)日：2015-03-26

    申请号：US14035508

    申请日：2013-09-24

    申请人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H04L9/30

    CPC分类号： H04L9/0631 ,  H04L2209/24

    摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

    摘要翻译： 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

    TRANSITION-AWARE SIGNALING
    20.
    发明申请
    TRANSITION-AWARE SIGNALING 失效
    过渡信号

    公开(公告)号：US20050030066A1

    公开(公告)日：2005-02-10

    申请号：US10389320

    申请日：2003-03-14

    申请人： Dennis Sylvester ,  Himanshu Kaul

    发明人： Dennis Sylvester ,  Himanshu Kaul

    IPC分类号： H03K3/3565 ,  H03K5/08 ,  H03K5/1534 ,  H03K5/22 ,  H04L25/02

    CPC分类号： H04L25/0292 ,  H03K3/3565 ,  H03K5/084 ,  H03K5/088 ,  H03K5/1534

    摘要： An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a transition signal in response to a detection of a transition from a first state to a second state on the interconnect line and further generates the transition signal in response to a detection of a transition from the second state to the first state on said interconnect line. The receiver further includes an output signal control circuit that, in response to the transition signal, selectively outputs either a present state of said interconnect line or a next state of the interconnect line stored in the receiver.

    摘要翻译： 公开了一种用于集成芯片上的改进的接收机电路。 接收器电路插入在集成电路中的电气部件之间的互连线中。 接收器电路具有转换检测电路，其响应于在互连线上从第一状态到第二状态的转变的检测而产生转换信号，并且响应于检测到来自第二状态的转变而产生转换信号 状态到所述互连线上的第一状态。 接收机还包括输出信号控制电路，响应于转换信号，选择性地输出所述互连线的当前状态或存储在接收机中的互连线的下一状态。