公开(公告)号：US06625685B1

公开(公告)日：2003-09-23

申请号：US09665989

申请日：2000-09-20

申请人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

发明人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

IPC分类号： G06F1200

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G06F12/0607

摘要： A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations. Furthermore, the portion of the address used to select between interleaved memory sections or interleaved channels may be programmable. One particular implementation may include all of the above programmable features, which may provide a high degree of flexibility in optimizing the memory system.

摘要翻译： 存储器控制器通过一个或多个配置寄存器为存储器的配置提供可编程的灵活性。 可以通过编程配置寄存器来为给定应用优化存储器。 例如，在一个实施例中，用于响应于存储器事务选择用于访问的存储位置的存储器事务的地址部分可以是可编程的。 在为DRAM设计的实现中，可编程地选择第一部分以形成行地址，并且第二部分可以被编程选择以形成列地址。 另外的实施例还可以包括用于选择银行的地址部分的可编程选择。 此外，在一些实现中，分配给不同芯片选择的存储器部分之间的交织模式和在存储器的两个或更多个通道中的交织模式可以是可编程的。 此外，用于在交织的存储器部分或交织的信道之间选择的地址的部分可以是可编程的。 一个具体实现可以包括所有上述可编程特征，其可以在优化存储器系统时提供高度的灵活性。

公开(公告)号：US20120233360A1

公开(公告)日：2012-09-13

申请号：US13474373

申请日：2012-05-17

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US08028103B2

公开(公告)日：2011-09-27

申请号：US12564610

申请日：2009-09-22

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US07836220B2

公开(公告)日：2010-11-16

申请号：US11505736

申请日：2006-08-17

申请人： Shailendra S. Desai ,  Mark D. Hayter ,  Dominic Go

发明人： Shailendra S. Desai ,  Mark D. Hayter ,  Dominic Go

IPC分类号： G06F13/28 ,  G06F15/16 ,  G06F15/167

CPC分类号： H04L49/35 ,  H04L49/109 ,  H04L49/352 ,  H04L69/324

摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

摘要翻译： 在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。 第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。 第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。 第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据 从数据链路层接收。 第二个节点被配置为将另一个分组处理到协议栈的顶部。

公开(公告)号：US07680963B2

公开(公告)日：2010-03-16

申请号：US11682065

申请日：2007-03-05

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US07320022B2

公开(公告)日：2008-01-15

申请号：US10202753

申请日：2002-07-25

申请人： Mark D. Hayter ,  Shailendra S. Desai ,  Daniel W. Dobberpuhl ,  Kwong-Tak A. Chui

发明人： Mark D. Hayter ,  Shailendra S. Desai ,  Daniel W. Dobberpuhl ,  Kwong-Tak A. Chui

IPC分类号： G06F13/00

CPC分类号： H04L47/30 ,  G06F13/128 ,  H04L45/00 ,  H04L45/60 ,  H04L47/29 ,  H04L49/103 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042

摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

摘要翻译： 分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。 在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。 在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。 特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。 当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

公开(公告)号：US06851004B2

公开(公告)日：2005-02-01

申请号：US10629097

申请日：2003-07-29

申请人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

发明人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/36

CPC分类号： G06F13/161

摘要： An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.

摘要翻译： 自适应重试机制可以记录近期事务的延迟（例如，第一数据传输等待时间），并且可以从两个或更多个重试延迟中选择重试延迟。 重试延迟可以用于事务，并且可以在事务中指定在第一数据传送尚未发生的情况下重试事务的时间点。 在一个实现中，该重试延迟集合包括最小重试延迟，标称重试延迟和最大重试延迟。 标称重试延迟可以被设置为略大于系统中事务的预期等待时间。 最小重试延迟可能小于标称重试延迟，并且最大重试延迟可能大于标称重试延迟。 如果正在经历大于标称重试延迟但小于最大重试延迟的延迟，则可以选择最大重试延迟。 另一方面，如果正在经历大于最大重试延迟的延迟，则可以选择最小重试延迟。

公开(公告)号：US20120297097A1

公开(公告)日：2012-11-22

申请号：US13566485

申请日：2012-08-03

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20120036289A1

公开(公告)日：2012-02-09

申请号：US13276537

申请日：2011-10-19

申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

公开(公告)号：US20100188980A1

公开(公告)日：2010-07-29

申请号：US12753466

申请日：2010-04-02

申请人： Shailendra S. Desai ,  Mark D. Hayter

发明人： Shailendra S. Desai ,  Mark D. Hayter

IPC分类号： H04L1/00

CPC分类号： H04L47/245 ,  H04L47/10 ,  H04L47/13

摘要： In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.

摘要翻译： 在一个实施例中，系统包括通信介质; 耦合到所述通信介质的第一控制器; 以及耦合到所述通信介质的第二控制器。 第一控制器被配置为在传送分组的第一部分之后中断在通信介质上的分组到第二控制器的传输。 第一控制器被配置为响应于中断分组的传输而在通信介质上发送至少一个控制符号，并且其中第一控制器被配置为继续使用分组的第二部分传输分组。 在一些实施例中，控制器可以包括媒体访问控制器和物理编码子层。