公开(公告)号：US20080140923A1

公开(公告)日：2008-06-12

申请号：US12031080

申请日：2008-02-14

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F12/00

CPC classification number: G11C11/40603 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C2207/2254

Abstract: A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

Abstract translation: 存储系统采用校准来确保数据的精确传输。 在校准期间，可能会发生内存刷新; 然而，这些刷新可能会干扰校准流。 因此，为了减轻碰撞和干扰，刷新推迟到不进行校准的时期。 还跟踪延期刷新的数量，以防止整体的刷新损失。

公开(公告)号：US07380052B2

公开(公告)日：2008-05-27

申请号：US10992378

申请日：2004-11-18

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/028

Abstract: A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract translation: 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

公开(公告)号：US07356642B2

公开(公告)日：2008-04-08

申请号：US10988313

申请日：2004-11-12

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F12/00

CPC classification number: G11C11/40603 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C2207/2254

Abstract: A method, an apparatus, and a computer program are provided to control refreshes in Extreme Data Rate (XDR™) memory systems. XDR™ memory systems employ calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

Abstract translation: 提供了一种方法，装置和计算机程序来控制极限数据速率（XDR TM）存储系统中的刷新。 XDR（TM）存储器系统采用校准来确保数据的精确传输。 在校准期间，可能会发生内存刷新; 然而，这些刷新可能会干扰校准流。 因此，为了减轻碰撞和干扰，刷新推迟到不进行校准的时期。 还跟踪延期刷新的数量，以防止整体的刷新损失。

公开(公告)号：US08219745B2

公开(公告)日：2012-07-10

申请号：US11002556

申请日：2004-12-02

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G06F13/1673

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract translation: 提供了一种方法，装置和计算机程序来解释存储在动态随机存取存储器（DRAM）写入缓冲器中的数据。 跟踪存储在DRAM写入缓冲器中的数据是困难的。 为了缓解困难，采用缓存行列表。 缓存行列表被保存在存储器控制器中，该存储器控制器被数据移动更新。 该列表允许轻松维护数据而不失一致性。

公开(公告)号：US07761682B2

公开(公告)日：2010-07-20

申请号：US12191195

申请日：2008-08-13

Applicant: Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

Inventor： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC: G06F13/14 ,  G06F13/36

CPC classification number: G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract translation: 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US20090119442A1

公开(公告)日：2009-05-07

申请号：US12349240

申请日：2009-01-06

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/06

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07490204B2

公开(公告)日：2009-02-10

申请号：US11101614

申请日：2005-04-07

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F13/1694

Abstract: A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.

Abstract translation: 存储器控制器设计工具检索由存储器控制器支持的参数范围，并识别麻烦的参数值组合。 内存控制器设计工具建议：1）向存储器控制器添加逻辑以解决冲突，2）结合一个约束，减少/消除命令冲突，数据冲突和/或需要检查特定的时序参数，或3） 两者的结合。 存储器控制器设计工具可以与存储器控制器设计器一起工作以定义和使用约束。

公开(公告)号：US20080307184A1

公开(公告)日：2008-12-11

申请号：US12191195

申请日：2008-08-13

Applicant: Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

Inventor： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract translation: 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US07305517B2

公开(公告)日：2007-12-04

申请号：US10988290

申请日：2004-11-12

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F13/00

CPC classification number: G06F13/1684 ,  G06F13/1689

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract translation: 提供了定序器的结构，方法和计算机程序，用于在XDR TM存储器系统中执行初始和周期性校准。 执行这些校准的存储器控​​制器被分成相同的独立半部，每个半部分包含电流/阻抗校准（i / z Cal）定序器和六个音序器。 i / z Cal序列器包含执行XIO电流和终止校准的三个路径，以及XDR（TM）DRAM电流和终端阻抗校准。 每个Bank序列器都包含正常的读写操作路径，用于实现接收建立，接收保持，发送设置，发送保持，XIO接收和XIO发送定时校准。 必须进行初始和周期性校准，以确保XIO和XDR（TM）DRAM之间数据的精确传输。

公开(公告)号：US07840744B2

公开(公告)日：2010-11-23

申请号：US11668725

申请日：2007-01-30

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

IPC: G06F12/00

CPC classification number: G06F13/1694

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。