公开(公告)号：US07467277B2

公开(公告)日：2008-12-16

申请号：US11348879

申请日：2006-02-07

申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC分类号： G06F13/14

CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US07761682B2

公开(公告)日：2010-07-20

申请号：US12191195

申请日：2008-08-13

申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US20080307184A1

公开(公告)日：2008-12-11

申请号：US12191195

申请日：2008-08-13

申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC分类号： G06F12/00

CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US07676639B2

公开(公告)日：2010-03-09

申请号：US12034681

申请日：2008-02-21

申请人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

发明人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

IPC分类号： G06F12/00

CPC分类号： G06F13/1673 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834

摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

摘要翻译： 提供了在XDR™存储系统中单独处理读写修改写命令的读写操作。 本发明允许系统在RMW的读取和写入之间发出其他命令。 这确保从读取到写入的数据流时间不是一个惩罚。 使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。 使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

公开(公告)号：US07716430B2

公开(公告)日：2010-05-11

申请号：US12033910

申请日：2008-02-20

申请人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

发明人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

IPC分类号： G06F12/00

CPC分类号： G06F13/1673 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834

摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

公开(公告)号：US07363442B2

公开(公告)日：2008-04-22

申请号：US10988314

申请日：2004-11-12

申请人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

发明人： Melissa Ann Barnum ,  Paul Allen Ganfield ,  Lonny Lambrecht

IPC分类号： G06F12/00

CPC分类号： G06F13/1673 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834

摘要： A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

摘要翻译： 提供了一种方法，装置和计算机程序，用于在XDR（TM）存储器系统中单独处理读取 - 修改 - 写入命令的读取和写入操作。 本发明允许系统在RMW的读取和写入之间发出其他命令。 这确保从读取到写入的数据流时间不是一个惩罚。 使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。 使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

公开(公告)号：US07321950B2

公开(公告)日：2008-01-22

申请号：US11050021

申请日：2005-02-03

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07487318B2

公开(公告)日：2009-02-03

申请号：US11851468

申请日：2007-09-07

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US20080168206A1

公开(公告)日：2008-07-10

申请号：US11620110

申请日：2007-01-05

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC分类号： G06F13/14

CPC分类号： G06F13/4059

摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

公开(公告)号：US20080183916A1

公开(公告)日：2008-07-31

申请号：US11668531

申请日：2007-01-30

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC分类号： G06F13/00

CPC分类号： G06F11/106

摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。