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公开(公告)号：US6094201A
公开(公告)日：2000-07-25
申请号：US57393
申请日：1998-04-08
CPC分类号： G06T15/80
摘要： A system and method of rendering polygons in graphics system using incremental iterative addition in place of complex division operations. A setup engine provides relevant values to edge and span walk modules for rapid processing and rendering of polygon characteristics including material values. Characteristic functions are iterated with respect to polygon area and along individual spans to derive values for each pixel therein.
摘要翻译： 使用增量迭代加法在图形系统中渲染多边形来代替复杂分割操作的系统和方法。 设置引擎为边缘和跨度步行模块提供相关值，用于快速处理和渲染包括材料值在内的多边形特征。 特征函数相对于多边形区域和沿着跨度迭代，以导出其中的每个像素的值。
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12.发明授权Array-word-organized display memory and address generator with time-multiplexed address bus 失效阵列字组织显示存储器和具有时间复用地址总线的地址发生器
公开(公告)号：US4773044A
公开(公告)日：1988-09-20
申请号：US933715
申请日：1986-11-21
申请人： Adrian Sfarti , Randy Goettsch
发明人： Adrian Sfarti , Randy Goettsch
IPC分类号： G09G5/00 , G06F3/153 , G06F12/00 , G06F12/06 , G06T1/60 , G09G1/02 , G09G5/36 , G09G5/39 , G09G5/395 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/18 , G11C11/401 , G06F13/00
摘要： An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.
摘要翻译： 一种阵列字组织的存储器系统，包括多个列和行的存储器芯片，通过所有存储器芯片布线的地址总线，多条可选择的CAS线，其中一条CAS线路经过所述多个 的存储器芯片的列和多个可选择的RAS线，其中RAS线之一被路由通过所述多行存储器芯片中的每一行。 在操作中，选择的X和Y地址与在四个连续时间段期间选择的CAS和RAS线的选通一起被施加到存储器芯片，用于寻址存储在存储器芯片中的任意阵列的像素。
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13.发明授权公开(公告)号：US08412916B2
公开(公告)日：2013-04-02
申请号：US12822258
申请日：2010-06-24
申请人： Adrian Sfarti , Korbin Van Dyke , Michael Frank , Arkadi Avrukin
发明人： Adrian Sfarti , Korbin Van Dyke , Michael Frank , Arkadi Avrukin
CPC分类号： G06F13/4027 , G06F2213/0038 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions.
摘要翻译： 也称为集成计算系统的集成电路具有沉积在其上或在其上蚀刻的单个衬底，中央处理单元，北桥，南桥和图形控制器。 内部总线连接在北桥和中央处理单元之间。 中央处理单元和北桥不需要接口来执行总线协议转换。
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公开(公告)号：USRE42534E1
公开(公告)日：2011-07-12
申请号：US12767997
申请日：2010-04-27
申请人： Adrian Sfarti
发明人： Adrian Sfarti
IPC分类号： G06T15/30
CPC分类号： G06T17/20
摘要： The present invention provides a graphics processing unit for rendering objects from a software application executing on a processing unit in which the objects to be rendered are received as control points of bicubic surfaces. According to the method and system disclosed herein, the graphics processing unit includes a transform unit, a lighting unit, a renderer unit, and a tessellate unit for tessellating both rational and non-rational object surfaces in real-time.
摘要翻译： 本发明提供一种图形处理单元，用于从在要呈现的对象被接收的处理单元上执行的软件应用程序呈现对象，作为双三次表面的控制点。 根据本文公开的方法和系统，图形处理单元包括变换单元，照明单元，渲染单元和镶嵌单元，用于实时地分解理性和非理性对象表面。
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公开(公告)号：US07295204B2
公开(公告)日：2007-11-13
申请号：US11013039
申请日：2004-12-14
申请人： Adrian Sfarti
发明人： Adrian Sfarti
IPC分类号： G06T17/20
CPC分类号： G06T17/205 , G06T17/20
摘要： A method and system is provided for rendering bicubic surfaces of an object on a computer system. Each bicubic surface is defined by sixteen control points and bounded by four boundary curves, each corresponding to an edge, and each boundary curve is formed by boundary box of line segments formed between four of the control points. The method and system of include transforming only the control points of the surface given a view of the object, rather than points across the entire bicubic surface, and using the four boundary edges for purposes of subdivision. Next, a pair of orthogonal boundary curves to process is selected. After the boundary curves have been selected, each of the curves is iteratively subdivided and the pair of orthogonal internal curves, wherein two new curves are generated with each subdivision. The subdivision of each of the curves is terminated when the curves satisfy a flatness threshold expressed in screen coordinates, whereby the number of computations required to render the object is minimized.
摘要翻译： 提供了一种用于在计算机系统上呈现物体的双立面的方法和系统。 每个双三次表面由十六个控制点定义，并且由四个边界曲线限定，每个边界对应于边缘，每个边界曲线由形成在四个控制点之间的线段的边界框形成。 该方法和系统包括只给出具有对象视图的表面的控制点，而不是跨整个双三次表面的点，并且为了细分目的使用四个边界边缘。 接下来，选择一对要处理的正交边界曲线。 在选择边界曲线后，每个曲线被迭代细分，并且一对正交内部曲线，其中每个细分生成两条新曲线。 当曲线满足以屏幕坐标表示的平坦度阈值时，每个曲线的细分被终止，由此使呈现对象所需的计算次数最小化。
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公开(公告)号：US07245299B2
公开(公告)日：2007-07-17
申请号：US10732398
申请日：2003-12-09
申请人： Adrian Sfarti
发明人： Adrian Sfarti
IPC分类号： G06T15/30
摘要： The present invention provides a graphics processing unit for rendering objects from a software application executing on a processing unit in which the objects to be rendered are transmitted to the graphics processing unit over a bus as control points of bicubic surfaces. According to the method and system disclosed herein, the graphics processing unit includes a transform unit, a lighting unit, a renderer unit, and a tessellate unit for tessellating both rational and non-rational object surfaces in real-time.
摘要翻译： 本发明提供了一种图形处理单元，用于从在待处理单元上执行的软件应用程序中的对象进行呈现，该处理单元通过总线作为二次表面的控制点传送到图形处理单元。 根据本文公开的方法和系统，图形处理单元包括变换单元，照明单元，渲染单元和镶嵌单元，用于实时地分解理性和非理性对象表面。
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17.发明授权
公开(公告)号：US6144387A
公开(公告)日：2000-11-07
申请号：US55094
申请日：1998-04-03
申请人： Mei-Chi Liu , Adrian Sfarti , Adam Malamy , Nicholas Baker , John Cumming
发明人： Mei-Chi Liu , Adrian Sfarti , Adam Malamy , Nicholas Baker , John Cumming
CPC分类号： G06T15/30
摘要： Performing graphics rendering without the computational expense of hither plane clipping and with only a minimum of display image clipping. Where a three dimensional polygon crosses to both sides of a hither plane, any vertices on the back side of the hither plane are translated to the hither plane, producing polygons which occupy only the area in front of the hither plane. A display image memory, from which display images are generated, is located within a larger guard memory such that many images which would need to be clipped to fit in the display image memory may be written to the guard memory without clipping.
摘要翻译： 执行图形渲染，而不需要平面裁剪的计算费用，只有最小的显示图像裁剪。 在三维多边形与两个平面的两侧相交的位置上，任一平面的背面上的任何顶点都被平移到两个平面，产生仅在该平面前面区域的多边形。 生成显示图像的显示图像存储器位于更大的保护存储器内，使得需要被剪切以适合显示图像存储器的许多图像可以被写入保护存储器而不会被削波。
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18.发明授权Inverse Z-buffer and video display system having list-based control mechanism for time-deferred instructing of 3D rendering engine that also responds to supervisory immediate commands 失效反向Z缓冲器和视频显示系统，具有基于列表的控制机制，用于延迟指示3D渲染引擎，也可响应监控立即命令
公开(公告)号：US5856829A
公开(公告)日：1999-01-05
申请号：US644870
申请日：1996-05-10
摘要： A graphics system includes triangle-engine for real-time rendering into a displayable frame-buffer of image data derived from vertex-based deferred instructions. The system uses homogeneity values (1/w values) for z-buffer-like occlusion mapping as well as for texture mapping. Depth resolution is enhanced for both occlusion mapping and texture mapping by representing (1/w), (u/w) and (v/w) values in a block-fixed format.
摘要翻译： 图形系统包括三角形引擎，用于实时呈现到从基于顶点的延迟指令导出的图像数据的可显示帧缓冲器中。 该系统使用同质性值（1 / w值）用于z-缓冲液状遮挡映射以及纹理映射。 通过以块固定格式表示（1 / w），（u / w）和（v / w）值来增强遮挡映射和纹理映射的深度分辨率。
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19.发明授权Apparatus and method for displaying characters in a bit mapped graphics system 失效用于在位映射图形系统中显示字符的装置和方法
公开(公告)号：US4622546A
公开(公告)日：1986-11-11
申请号：US564970
申请日：1983-12-23
申请人： Adrian Sfarti , Steven Dines
发明人： Adrian Sfarti , Steven Dines
摘要： An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for the storage of character descriptive information which includes an address table 26, macro-instructions 28, 30, and 32, and character bit maps 34, 36, and 38. Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.
摘要翻译： 公开了一种用于位映射图形显示系统中的字符和图形模式生成的装置和方法，其包括用于将字符位图和图形模式提供给可视显示存储器22的像素数据管理器14.字符信息存储器24用于 存储包括地址表26，宏指令28,30和32以及字符位图34,36和38的字符描述信息。一组字符中的每个字符具有相关联的宏指令和字符位 地图。 地址表包含指向宏指令的内存地址。 每个宏指令都包含建立相应字符位图的大小和位置的可执行指令。 为了向可视显示存储器提供字符，像素数据管理器取出并执行相应的宏指令。 中央处理单元的间接负担最小化。
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公开(公告)号：US4514673A
公开(公告)日：1985-04-30
申请号：US564979
申请日：1983-12-23
申请人： Adrian Sfarti
发明人： Adrian Sfarti
CPC分类号： H02P8/14
摘要： A stepper motor controller, for use with a main computer having vector interrupt capability, includes main address and data terminals, interrupt terminals, a select/enable terminal and control terminals, and is used to control the operation of a stepper motor pursuant to instructions from the main computer. The main computer enables a selected controller to accept commands or data through a decoder coupled to the select terminal. The controllers provide accept and error interrupt signals to the main computer when it is ready to receive data and to notify the main computer when an error condition is found. The controller generates a controller identifier message at its data terminals substantially simultaneously with the production of the interrupt signals to identify which controller is generating the interrupt signal. This eliminates the need for the main computer to poll the controllers.
摘要翻译： 步进电机控制器，与具有向量中断能力的主计算机一起使用，包括主地址和数据端子，中断端子，选择/使能端子和控制端子，并用于根据指令从 主电脑。 主计算机使所选择的控制器能够通过耦合到选择终端的解码器接受命令或数据。 控制器在准备好接收数据时向主计算机提供接受和错误中断信号，并在发现错误条件时通知主计算机。 控制器在其数据终端上产生与产生中断信号基本同时的控制器标识符消息，以识别哪个控制器正在产生中断信号。 这样就无需主计算机轮询控制器。
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