公开(公告)号：US20080019167A1

公开(公告)日：2008-01-24

申请号：US11833034

申请日：2007-08-02

Applicant: Trung Doan ,  D. Durcan ,  Brent Gilgen

Inventor： Trung Doan ,  D. Durcan ,  Brent Gilgen

IPC: G11C11/00 ,  H01L29/04

CPC classification number: H01L45/06 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract translation: 公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。 这种存储器件包括包括非平行侧壁的下电极。 绝缘材料覆盖下电极，使得下电极的上表面露出。 在一个实施例中，绝缘材料和下电极可以具有共面上表面。 在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。 硫族化物材料和上电极形成在下电极的上表面上。 这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

公开(公告)号：US20070138526A1

公开(公告)日：2007-06-21

申请号：US11669840

申请日：2007-01-31

Applicant: Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

Inventor： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

IPC: H01L29/94

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

公开(公告)号：US20070128856A1

公开(公告)日：2007-06-07

申请号：US11670296

申请日：2007-02-01

Applicant: Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

Inventor： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

IPC: H01L21/4763

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

公开(公告)号：US20060258162A1

公开(公告)日：2006-11-16

申请号：US11492323

申请日：2006-07-24

Applicant: Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

Inventor： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US20060046484A1

公开(公告)日：2006-03-02

申请号：US10934778

申请日：2004-09-02

Applicant: Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

Inventor： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US20050191819A1

公开(公告)日：2005-09-01

申请号：US10627468

申请日：2003-07-25

Applicant: Tyler Lowrey ,  Luan Tran ,  Alan Reinberg ,  D. Durcan

Inventor： Tyler Lowrey ,  Luan Tran ,  Alan Reinberg ,  D. Durcan

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/00 ,  H01L21/20

CPC classification number: H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract translation: 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。