公开(公告)号：US20190214556A1

公开(公告)日：2019-07-11

申请号：US15867159

申请日：2018-01-10

申请人： Winbond Electronics Corp.

发明人： Frederick CHEN ,  Ping-Kun WANG ,  Chih-Cheng FU ,  Chien-Min WU ,  Shao-Ching LIAO

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/08 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641

摘要： A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.

公开(公告)号：US20190198753A1

公开(公告)日：2019-06-27

申请号：US16293116

申请日：2019-03-05

申请人： SK hynix Inc.

发明人： Jin-Won Park

IPC分类号： H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  G06F3/06

CPC分类号： H01L43/08 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/161 ,  G11C13/0002 ,  G11C2213/52 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

摘要： Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.

公开(公告)号：US20190148635A1

公开(公告)日：2019-05-16

申请号：US16225318

申请日：2018-12-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen

发明人： Vara S. P. Jonnalagadda ,  Benedikt J. Kersting ,  Wabe W. Koelmans ,  Martin Salinga ,  Abu Sebastian

IPC分类号： H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/52 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148

摘要： The invention is directed to a resistive memory device comprising a control unit for controlling a memory cell of the memory device. The memory cell includes a first terminal, a second terminal and a phase change segment comprising a phase-change material. The phase change segment is arranged between the first terminal and the second terminal. The phase change material is antimony. The phase change segment retains an amorphous region during a write operation. The control unit, during the write operation, applies an electrical programming pulse to the terminals to cause a portion of the phase change segment to transition from a crystalline phase to an amorphous phase comprising the amorphous region. A trailing edge duration of the electrical programming pulse is adjusted based on ambient temperature to prevent re-crystallization of the amorphous region. Shorter trailing edge durations are used at increasing ambient temperatures.

公开(公告)号：US20180331282A1

公开(公告)日：2018-11-15

申请号：US15594498

申请日：2017-05-12

申请人： United Microelectronics Corp.

发明人： Mengkai Zhu

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1233 ,  G11C13/0002 ,  G11C2213/52 ,  H01L27/2409 ,  H01L45/1253 ,  H01L45/16

摘要： A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.

公开(公告)号：US20180309075A1

公开(公告)日：2018-10-25

申请号：US15496740

申请日：2017-04-25

申请人： International Business Machines Corporation

发明人： Kevin W. Brew ,  Guy M. Cohen ,  Talia S. Gershon ,  Yun Seog Lee ,  Ning Li ,  Devendra K. Sadana

IPC分类号： H01L51/10 ,  H01L51/05 ,  H01L51/00 ,  G11C13/00

CPC分类号： H01L51/102 ,  G11C11/5664 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0092 ,  G11C2213/52 ,  H01L51/0003 ,  H01L51/0008 ,  H01L51/0591 ,  H01L51/105 ,  H01L2251/301

摘要： Memristive devices based on tunable Schottky barrier are provided. In one aspect, a method of forming a memristive device includes: forming a semiconductor layer on a bottom metal electrode, wherein the semiconductor layer has workfunction-modifying molecules embedded therein; and forming a top metal electrode on the semiconductor layer, wherein the top metal electrode forms a Schottky junction with the semiconductor layer, and wherein the workfunction-modifying molecules are configured to alter a workfunction of the top metal electrode. A memristive device and a method for operating a memristive device are also provided.

公开(公告)号：US20180040814A1

公开(公告)日：2018-02-08

申请号：US15469266

申请日：2017-03-24

申请人： SK hynix Inc.

发明人： Jin-Won Park

IPC分类号： H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G06F3/06 ,  H01L43/02 ,  H01L27/22

CPC分类号： H01L43/08 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/161 ,  G11C13/0002 ,  G11C2213/52 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

摘要： Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.

公开(公告)号：US20170309332A1

公开(公告)日：2017-10-26

申请号：US15138477

申请日：2016-04-26

申请人： HGST Netherlands B.V.

发明人： Daniel Bedau

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/528 ,  H01L27/2481 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658

摘要： To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.

公开(公告)号：US09754665B2

公开(公告)日：2017-09-05

申请号：US15228216

申请日：2016-08-04

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yangyin Chen ,  Christopher J. Petti ,  Kun Hou

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/55 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1675

摘要： A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

公开(公告)号：US20170221559A1

公开(公告)日：2017-08-03

申请号：US15228216

申请日：2016-08-04

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yangyin Chen ,  Christopher J. Petti ,  Kun Hou

IPC分类号： G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/55 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1675

摘要： A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

公开(公告)号：US20170179382A1

公开(公告)日：2017-06-22

申请号：US15374957

申请日：2016-12-09

申请人： Microsemi SoC Corporation

发明人： John L. McCollum ,  Fethi Dhaoui ,  Frank W. Hawley

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/085 ,  G11C13/0011 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/11 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/54 ,  G11C2213/56 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.