公开(公告)号：US5510630A

公开(公告)日：1996-04-23

申请号：US138908

申请日：1993-10-18

申请人： Anant K. Agarwal ,  Richard R. Siergiej ,  Charles D. Brandt ,  Marvin H. White

发明人： Anant K. Agarwal ,  Richard R. Siergiej ,  Charles D. Brandt ,  Marvin H. White

IPC分类号： H01L21/82 ,  H01L27/115 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/04 ,  H01L29/48

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L27/115 ,  H01L29/7838

摘要： A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

摘要翻译： 利用简单的单晶体管DRAM单元配置的非易失性随机存取存储器（NVRAM）单元。 目前的NVRAM采用了作为累积模式晶体管制成的增强型nMOS晶体管。 晶体管在p型碳化硅缓冲层上具有n型碳化硅沟道层，其中沟道和缓冲层位于高电阻碳化硅衬底上。 晶体管还在沟道层上具有n +源极和漏极接触区域。 优选使用具有非常低的漏电流的多晶硅/氧化物/金属电容器。 此外，这种类型的电容器可以堆叠在晶体管的顶部以节省面积并实现高电池密度。 优选使用不可重入（无边缘）栅极晶体管结构来进一步减少边缘效应。

公开(公告)号：US4253168A

公开(公告)日：1981-02-24

申请号：US953810

申请日：1978-10-23

申请人： Kenneth J. Petrosky ,  Marvin H. White

发明人： Kenneth J. Petrosky ,  Marvin H. White

IPC分类号： G10K11/34 ,  H01L27/105 ,  H03H15/02 ,  H03H7/20 ,  G01S3/80

CPC分类号： H03H15/02 ,  G10K11/345 ,  H01L27/1057

摘要： Apparatus for forming one or more sonar beams in response to acoustic energy received by a transducer array. To minimize volume utilization, a plurality of CCD's are formed on an integrated circuit chip with the CCD's being of progressively smaller length. Half of the CCD array is folded over to match the other half so that each CCD has an opposing CCD with both CCD's propagating a signal toward a common output diode. By providing one integrated circuit chip for each desired beam with appropriately different clocking frequencies multiple beams may be formed, and with the provision of a variable clocking frequency, one or more beams may be steered.Transversal filter operations may also be performed by the apparatus.

摘要翻译： 用于响应于由换能器阵列接收的声能形成一个或多个声纳束的装置。 为了最小化体积利用率，在集成电路芯片上形成多个CCD，CCD的长度逐渐变小。 CCD阵列的一半被折叠以匹配另一半，使得每个CCD具有相对的CCD，两个CCD将信号传播到公共输出二极管。 通过为每个期望的波束提供具有适当不同的时钟频率的一个集成电路芯片，可以形成多个波束，并且通过提供可变的时钟频率，可以控制一个或多个波束。 横向滤波器操作也可以由该装置执行。

公开(公告)号：US4053917A

公开(公告)日：1977-10-11

申请号：US714412

申请日：1976-08-16

申请人： Franklyn C. Blaha ,  James R. Cricchi ,  Marvin H. White

发明人： Franklyn C. Blaha ,  James R. Cricchi ,  Marvin H. White

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/32 ,  H01L29/786 ,  H01L29/792 ,  H01L29/78 ,  H01L29/34 ,  H01L49/02

CPC分类号： H01L21/32 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/78606 ,  H01L29/78657 ,  H01L29/792

摘要： An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

摘要翻译： 改进的漏极保护的MNOS晶体管通过允许对存储器和非存储器参数的独立控制的制造技术来实现。 在制造期间通过使用氮化物掩模进行栅极氧化来实现存储区域的自对准。 存储器和非存储器参数的独立控制源于其中受保护区域仅由栅氧化物组成的器件配置，并且氮化硅仅存在于存储器区域中。 也可以通过消除器件的薄二氧化硅区域上的氮化物层来实现晶体管辐射硬化。

公开(公告)号：US4042945A

公开(公告)日：1977-08-16

申请号：US595458

申请日：1975-07-14

申请人： Hung C. Lin ,  Marvin H. White

发明人： Hung C. Lin ,  Marvin H. White

IPC分类号： H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

CPC分类号： H01L29/513 ,  H01L29/1087 ,  H01L29/78 ,  H01L29/517 ,  H01L29/518

摘要： An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.

摘要翻译： 其中两层不同介电材料（例如，二氧化硅和氮化硅）与P掺杂硅栅极结合使用以允许使用更高电阻率的P型衬底的N沟道MOS晶体管。 这使得能够在栅极和衬底之间的功函数差异增加的情况下，更高的结击穿电压和更高的阈值电压在衬底上没有反向偏置。 由于衬底的较低的浓度（即较高的电阻率），由于较低的漏 - 源电容而导致高频响应增加。