公开(公告)号：US4053917A

公开(公告)日：1977-10-11

申请号：US714412

申请日：1976-08-16

申请人： Franklyn C. Blaha ,  James R. Cricchi ,  Marvin H. White

发明人： Franklyn C. Blaha ,  James R. Cricchi ,  Marvin H. White

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/32 ,  H01L29/786 ,  H01L29/792 ,  H01L29/78 ,  H01L29/34 ,  H01L49/02

CPC分类号： H01L21/32 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/78606 ,  H01L29/78657 ,  H01L29/792

摘要： An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

摘要翻译： 改进的漏极保护的MNOS晶体管通过允许对存储器和非存储器参数的独立控制的制造技术来实现。 在制造期间通过使用氮化物掩模进行栅极氧化来实现存储区域的自对准。 存储器和非存储器参数的独立控制源于其中受保护区域仅由栅氧化物组成的器件配置，并且氮化硅仅存在于存储器区域中。 也可以通过消除器件的薄二氧化硅区域上的氮化物层来实现晶体管辐射硬化。

公开(公告)号：US4096509A

公开(公告)日：1978-06-20

申请号：US707574

申请日：1976-07-22

申请人： Franklyn C. Blaha ,  James R. Cricchi

发明人： Franklyn C. Blaha ,  James R. Cricchi

IPC分类号： H01L21/86 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

CPC分类号： H01L29/513 ,  H01L21/86 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/78606 ,  H01L29/78657 ,  H01L29/792 ,  Y10S148/018 ,  Y10S148/02 ,  Y10S148/082 ,  Y10S148/15

摘要： A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.

摘要翻译： 采用利用两个单独的氮化硅沉积（一个形成存储区，第二个形成非存储区）的处理技术来提供辐射硬源漏保护的存储晶体管。 在非记忆区域中使用的二氧化硅的量也被最小化。 典型的器件包括从其中植入P +源极和漏极区的硅蓝宝石（SOS）晶片蚀刻的台面。 二氧化硅100 A层和第二层1000A非记忆氮化硅层覆盖台面，蚀刻两层以限定衬底栅极窗口。 门窗被25 A隧道氧化层覆盖A最终500 A层的记忆氮化硅覆盖了台面结构。 接触窗被蚀刻以适应源极，漏极和栅极互连电极。

公开(公告)号：US4148049A

公开(公告)日：1979-04-03

申请号：US765484

申请日：1977-02-04

申请人： James R. Cricchi ,  Franklyn C. Blaha ,  Michael D. Fitzpatrick

发明人： James R. Cricchi ,  Franklyn C. Blaha ,  Michael D. Fitzpatrick

IPC分类号： H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/78 ,  H01L29/792

摘要： A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer.A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

摘要翻译： 公开了辐射硬化的漏极 - 源极保护的MNOS晶体管。 氧化硅层覆盖沟道和由漏极和源极区域与沟道的交点形成的结。 漏极和源极保护由氧化硅层的相对较厚的部分提供，其覆盖由漏极和源极区域以及沟道形成的结。 覆盖通道中心部分的氧化硅层的部分比该层的其余部分薄。

公开(公告)号：USRE30087E

公开(公告)日：1979-08-28

申请号：US642032

申请日：1975-12-18

申请人： Marvin H. White ,  David H. McCann, Jr. ,  Ingham A. G. Mack ,  Franklyn C. Blaha

发明人： Marvin H. White ,  David H. McCann, Jr. ,  Ingham A. G. Mack ,  Franklyn C. Blaha

IPC分类号： G11C19/28 ,  G11C27/04 ,  H01L27/148 ,  H01L29/768

CPC分类号： G11C27/04 ,  G11C19/285 ,  H01L27/14831 ,  H01L29/76816

摘要： A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing subintervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.