公开(公告)号：US20100078762A1

公开(公告)日：2010-04-01

申请号：US12630337

申请日：2009-12-03

Applicant: Wensheng Wang

Inventor： Wensheng Wang

IPC: H01L29/92 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L28/75 ,  H01L27/1057 ,  H01L27/11507 ,  H01L28/56

Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.

Abstract translation: 在半导体器件制造方法中，在优先沿着预定的晶面取向的第一金属膜上形成非晶或微晶金属氧化物膜。 之后，通过MOCVD法形成铁电体膜。 当形成铁电体膜时，在第一金属膜上形成的金属氧化物膜被还原为第二金属膜，并且铁电体膜形成在第二金属膜上。 当形成铁电体膜时，非晶或微晶金属氧化物膜容易均匀地被还原。 结果，获得其取向良好的第二金属膜，并且在第二金属膜上形成其取向良好的铁电体膜。 在形成铁电体膜之后，在铁电体膜上形成上部电极。

公开(公告)号：US20090096028A1

公开(公告)日：2009-04-16

申请号：US12085866

申请日：2006-12-01

Applicant: Cyrille Le Royer ,  Olivier Faynot ,  Laurent Clavelier

Inventor： Cyrille Le Royer ,  Olivier Faynot ,  Laurent Clavelier

IPC: H01L27/088

CPC classification number: H01L27/1057 ,  H01L29/7391

Abstract: The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric field in the intermediate zone (I), on the same side as the first junction (3), and a second gate (6) to generate an electric field in the intermediate zone (I), on the same side as the second junction (4).

Abstract translation: 晶体管包括由轻掺杂中间区（I）分离的源（1）和漏极（2）。 中间区域（I）分别与源极（1）和漏极（2）形成第一（3）和第二（4）结。 晶体管包括在与第一结（3）相同的一侧在中间区（I）中产生电场的第一栅极（5）和在中间区域中产生电场的第二栅极（6） （I），与第二结（4）相同。

公开(公告)号：US06518070B1

公开(公告)日：2003-02-11

申请号：US09571586

申请日：2000-05-17

Applicant: Prasad V. Alluri ,  Mark Victor Raymond ,  Sucharita Madhukar ,  Roland R. Stumpf ,  Chun-Li Liu ,  Clarence J. Tracy

Inventor： Prasad V. Alluri ,  Mark Victor Raymond ,  Sucharita Madhukar ,  Roland R. Stumpf ,  Chun-Li Liu ,  Clarence J. Tracy

IPC: H01L2170

CPC classification number: H01L21/3212 ,  H01L27/1057 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65

Abstract: A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.

Abstract translation: 用于在半导体器件内形成具有高k电介质层或铁电体层的电容器的工艺被用于降低该层与下层之间的氧化或材料相互作用的可能性。 第一电极层包括沿第一电极层内的晶界形成的原子，以减少导电塞的氧化或不期望的材料相互作用。

公开(公告)号：US5260228A

公开(公告)日：1993-11-09

申请号：US977836

申请日：1992-11-17

Applicant: Minoru Taguchi

Inventor： Minoru Taguchi

IPC: H01L27/06 ,  H01L27/105 ,  H01L21/70

CPC classification number: H01L27/0623 ,  H01L27/1057

Abstract: A semiconductor device having a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on a major surface of the semiconductor substrate, an isolation layer of the first conductivity type formed in the epitaxial layer and extending from a surface thereof to the major surface of the semiconductor substrate. The isolation layer divides the epitaxial layer into first, second, and third islands. The device further has two wells of the first conductivity type, formed in the first and second islands, respectively, and extending to the substrate, a charge transfer device having a back gate formed of the first well, an insulated-gate FET of the first conductivity type, having a back gate formed of the second island, an insulated-gate FET of the second conductivity type, having a back gate formed of the second well, and a bipolar transistor having a collector formed of the third island. The first island surrounds the first well which serves as back gate of the charge transfer device, and thus blocks the noise generated in the first well. Hence, the other islands are free from the influence of the noise.

Abstract translation: 一种半导体器件，具有第一导电类型的半导体衬底，形成在半导体衬底的主表面上的第二导电类型的外延层，形成在外延层中并从其表面延伸的第一导电类型的隔离层 到半导体衬底的主表面。 隔离层将外延层划分成第一岛，第二岛和第三岛。 该器件还具有分别形成在第一和第二岛中并且延伸到衬底的第一导电类型的两个阱，具有由第一阱形成的背栅的电荷转移器件，第一阱的绝缘栅FET 具有由第二岛形成的背栅的导电类型，具有由第二阱形成的背栅的第二导电类型的绝缘栅FET，以及具有由第三岛形成的集电极的双极晶体管。 第一岛围绕作为电荷转移装置的背栅的第一阱，从而阻止在第一阱中产生的噪声。 因此，其他岛屿没有噪音的影响。

公开(公告)号：US4903097A

公开(公告)日：1990-02-20

申请号：US831881

申请日：1986-02-24

Applicant: Greg Nash

Inventor： Greg Nash

IPC: G11C17/04 ,  H01L27/105 ,  H01L29/10

CPC classification number: H01L27/1057 ,  G11C17/04 ,  H01L29/1062

Abstract: The specification describes a high capacity nonvolatile CCD read only memory system that includes a plurality of memory cells. Selected ones of the memory cells include a double-diffused region having a first and second implant or diffusion under a clocked electrode whereby the first implant or diffusion provides a fixed charge required for ROM operation and the charge and polarity of said second implant or diffusion provides a neutralizing effect on the surface potential under the clocked electrode and above the double implanted or double diffused region.

Abstract translation: 本说明书描述了包括多个存储单元的高容量非易失性CCD只读存储器系统。 所选择的存储单元包括在时钟电极下具有第一和第二注入或扩散的双扩散区域，由此第一注入或扩散提供ROM操作所需的固定电荷，并且所述第二注入或扩散的电荷和极性提供 对时钟电极下方的表面电位和双注入或双扩散区域以上的中和作用。

公开(公告)号：US4807005A

公开(公告)日：1989-02-21

申请号：US254672

申请日：1981-04-16

Applicant: Leonard J. M. Esser ,  Gijsbert Lock

Inventor： Leonard J. M. Esser ,  Gijsbert Lock

IPC: H04N5/335 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L27/00 ,  H01L27/105 ,  H01L27/148 ,  H01L29/10 ,  H01L29/762 ,  H01L29/768 ,  H01L27/04

CPC classification number: H01L29/1062 ,  G11C19/282 ,  G11C27/04 ,  H01L27/1057 ,  H01L29/76833

Abstract: The present invention involves a semiconductor device, such as a shift register, wherein information in the form of charge carriers is moved laterally through the bulk of a semiconductor layer by means of an electric field, while the charge carriers are stored at the surface of the semiconductor layer. According to this invention, information containing regions can be separated from each other by depletion zones extending through the thickness and the width of the semiconductor layer. Charge transport laterally through the interior of the semiconductor layer results in a considerable reduction of the transport time. Majority charge carriers are advantageously used.

Abstract translation: 本发明涉及诸如移位寄存器的半导体器件，其中电荷载体形式的信息通过电场横向移动穿过半导体层的主体，而电荷载体被存储在 半导体层。 根据本发明，包含区域的信息可以通过延伸穿过半导体层的厚度和宽度的耗尽区彼此分离。 横向穿过半导体层的内部的电荷输送导致运输时间的显着降低。 有利地使用多数电荷载体。

公开(公告)号：US4412344A

公开(公告)日：1983-10-25

申请号：US161134

申请日：1980-06-19

Applicant: Manfred Mauthe ,  Hans-Jorg Pfleiderer

Inventor： Manfred Mauthe ,  Hans-Jorg Pfleiderer

IPC: G11C27/04 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H01L29/768 ,  H02M7/21 ,  G11C19/28 ,  H01L29/78

CPC classification number: H01L29/76808 ,  H01L27/1057

Abstract: An integrated rectifier circuit has a doped semiconductor body having first and second oppositely doped regions therein and is covered by an electrically insulating layer on which a first pair of input gate electrodes are disposed which are associated with the first oppositely doped region and on which a second pair of input gate electrodes are disposed associated with the second oppositely doped region. The oppositely doped regions are connected to a clock pulse voltage and all of the input gate electrodes are connected to a constant voltage having a magnitude such that a uniform surface potential exists in the semiconductor regions covered by the electrodes. The input gate electrode of the first pair which is disposed at a greater distance from the first oppositely doped region and the input gate electrode of the second pair which is disposed closer to the second oppositely doped region are charged with the alternating voltage component of an input signal. A charge transfer device transfer channel covered with transfer electrodes is connected to the semiconductor regions covered by the input electrodes and a charge transfer device output stage couples an output signal to external circuitry in which the alternating voltage component is rectified.

Abstract translation: 集成整流器电路具有掺杂半导体本体，其中具有第一和第二相对掺杂区域，并被电绝缘层覆盖，电绝缘层上设置有与第一相对掺杂区域相关联的第一对输入栅电极， 一对输入栅电极设置成与第二相对掺杂区域相关联。 相对掺杂的区域连接到时钟脉冲电压，并且所有输入栅电极连接到具有使得在由电极覆盖的半导体区域中存在均匀表面电位的量级的恒定电压。 设置在离第一相对掺杂区域更远的距离处的第一对的输入栅极电极和靠近第二相对掺杂区域设置的第二对的输入栅电极被充满输入的交流电压分量 信号。 由传输电极覆盖的电荷转移装置传输通道连接到由输入电极覆盖的半导体区域，并且电荷转移装置输出级将输出信号耦合到交流电压分量被整流的外部电路。

公开(公告)号：US4364076A

公开(公告)日：1982-12-14

申请号：US828080

申请日：1977-08-26

Applicant: Pallab K. Chatterjee ,  Aloysious F. Tasch, Jr.

Inventor： Pallab K. Chatterjee ,  Aloysious F. Tasch, Jr.

IPC: G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H01L29/78 ,  G11C11/34

CPC classification number: H01L27/1057 ,  G11C19/287

Abstract: A charge coupled device memory is disclosed which includes a plurality of stages having increased charged storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under the phase electrodes is divided into barrier regions and adjacent well regions bounded by the channel. A dopant layer of a second-type conductivity lies in each of the well regions relatively near to the first surface. An enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions relatively far from the surface having a doping which is greater than the doping of the first-type conductivity semiconductor substrate.

Abstract translation: 公开了一种电荷耦合器件存储器，其包括具有增加的充电存储容量和减小的漏电流的多个级。 每个级由具有第一表面的第一类型导电性半导体衬底组成。 均匀厚度的绝缘层位于第一表面上。 电荷转移通道延伸穿过每个阶段。 相位电极位于绝缘层上横向于通道。 相电极下面的半导体衬底被分成由通道限定的阻挡区域和相邻阱区域。 第二类型导电性的掺杂剂层位于相对靠近第一表面的每个阱区中。 增强的第一类型导电性掺杂剂层位于阱区域中，并且与具有大于第一类型导电性半导体衬底的掺杂的掺杂的表面相对较远的势垒区域。

公开(公告)号：US4321481A

公开(公告)日：1982-03-23

申请号：US153712

申请日：1980-05-27

Applicant: Jerome J. Tiemann

Inventor： Jerome J. Tiemann

IPC: G11C19/28 ,  H01L27/105 ,  H03H15/02 ,  H01L29/78

CPC classification number: G11C19/282 ,  H01L27/1057 ,  H03H15/02

Abstract: A filter utilizing charge transfer devices for providing recursive transfer functions with a transmission zero at d.c. or zero frequency is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, and first, second, third and fourth linear charge transfer shift registers. All five shift registers are clocked at the same frequency. A first input sequence of packets of charge representing positive weight components of a signal, and a second sequence of packets of charge representing negative weight components of the signal are provided. Means are provided for dividing each of the packets of charge of the first input sequence into a first part and a second part and for applying each of the first parts of the packets of the first input sequence to the input stage of the first shift register and for applying each of the second parts of the packets of the first input sequence to the input stage of the second shift register. The charge packet in the first charge storage cell in the K.sup.th stage of the first shift register is combined with the charge packet in the first charge storage cell of the N.sup.th stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the K.sup.th stage of the first shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the N.sup.th stage of the circular shift register. The charge packet in the first charge storage cell of the L.sup.th stage of the second shift register is combined with the charge packet in the M.sup.th stage of the circular shift register, where M is an integer less than N/2 and L=K+M.Means are provided for dividing each of the packets of charge of the second input sequence into a first part and a second part and for applying each of the first parts of the packets of the second input sequence to the input stage of the third shift register and for applying each of the second parts of the packets of the second input sequence to the input stage of the fourth shift register. The charge packet in the first charge storage cell in the K.sup.th stage of the third shift register is combined with the charge packet in the first charge storage cell of the (N/2).sup.th stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the K.sup.th stage of the third shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the (N/2).sup.th stage of the circular shift register. The charge packet in the first charge storage cell of the L.sup.th stage of the fourth shift register is combined with the charge packet in the (N/2+M).sup.th stage of the circular shift register.A first output sequence of packets of charge representing the positive components of an output signal is obtained at the output of the first shift register. A second output sequence of packets of charge representing the negative components of the output signal is obtained at the output of the second shift register. The output signal is obtained by differentially summing corresponding charge packets in the first and second output sequences.

公开(公告)号：US4316100A

公开(公告)日：1982-02-16

申请号：US143130

申请日：1980-04-23

Applicant: Tatsuo Sakaue ,  Tetsuya Iida

Inventor： Tatsuo Sakaue ,  Tetsuya Iida

IPC: G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L27/105 ,  H01L27/148 ,  H01L29/762 ,  H03H15/02 ,  H04N5/21 ,  H01L29/78

CPC classification number: H03H15/02 ,  G11C19/285 ,  G11C27/04 ,  H01L27/1057 ,  H04N5/211

Abstract: Disclosed is a charge transfer device, like a transversal filter, having means for detecting if an amount of signal charge transferred from one stage to another falls within a dynamic range of the device. A charge transfer channel is so formed as to have first and second branched output ports. A signal charge transferred to the first output port is detected as an output signal supplied to a utilization circuit while an output voltage caused by a signal charge transferred to the second output port is compared with first and second reference voltages which correspond to first and second amounts of signal charges substantially determining upper and lower limits of the dynamic range of the device, whereby it is detected if the amount of the signal charge transferred is within the dynamic range or not. As a result of the detection when the signal charge amount is outside the dynamic range, the supply of the output signal to the utilization circuit is interrupted.

Abstract translation: 公开了一种电荷转移装置，如横向滤波器，具有用于检测从一个级传送到另一级的信号电荷量是否落入该装置的动态范围内的装置。 电荷转移通道形成为具有第一和第二分支输出端口。 将传送到第一输出端口的信号电荷作为提供给利用电路的输出信号进行检测，同时将由转移到第二输出端口的信号电荷引起的输出电压与对应于第一和第二量的第一和第二参考电压进行比较 信号电荷基本上决定了装置的动态范围的上限和下限，从而检测到所传输的信号电荷量是否在动态范围内。 当信号电荷量在动态范围之外时，作为检测的结果，中断了向利用电路的输出信号的供给。