公开(公告)号：US09640609B2

公开(公告)日：2017-05-02

申请号：US12037211

申请日：2008-02-26

申请人： Qingchun Zhang ,  Charlotte Jonas ,  Anant K. Agarwal

发明人： Qingchun Zhang ,  Charlotte Jonas ,  Anant K. Agarwal

IPC分类号： H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L29/872

CPC分类号： H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/872

摘要： Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

公开(公告)号：US09312343B2

公开(公告)日：2016-04-12

申请号：US12577929

申请日：2009-10-13

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant K. Agarwal ,  Sarit Dhar

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant K. Agarwal ,  Sarit Dhar

IPC分类号： H01L29/267 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423

CPC分类号： H01L29/7802 ,  H01L29/04 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7813

摘要： A transistor may include a semiconductor drift layer of a first semiconductor material and a semiconductor channel layer on the semiconductor drift layer. The semiconductor channel layer may include a second semiconductor material different than the first semiconductor material. A semiconductor interconnection layer may be electrically coupled between the semiconductor drift layer and the semiconductor channel layer, and the semiconductor interconnection layer may include a third semiconductor material different than the first and second semiconductor materials. In addition, a control electrode may be provided on the semiconductor channel layer.

摘要翻译： 晶体管可以包括第一半导体材料的半导体漂移层和半导体漂移层上的半导体沟道层。 半导体沟道层可以包括与第一半导体材料不同的第二半导体材料。 半导体互连层可以电耦合在半导体漂移层和半导体沟道层之间，并且半导体互连层可以包括不同于第一和第二半导体材料的第三半导体材料。 此外，可以在半导体沟道层上设置控制电极。

公开(公告)号：US08901699B2

公开(公告)日：2014-12-02

申请号：US11126816

申请日：2005-05-11

申请人： Sei-Hyung Ryu ,  Anant K. Agarwal

发明人： Sei-Hyung Ryu ,  Anant K. Agarwal

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/6606 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/872

摘要： Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact. The second region of silicon carbide has a second doping concentration that is less than the first doping concentration.

摘要翻译： 提供阻塞内部PiN二极管在结屏障肖特基（JBS）结构中的电流传导的积分结构。 肖特基二极管可以与PiN二极管串联，其中肖特基二极管与PiN二极管的方向相反。 可以在PiN二极管和肖特基接触之间提供串联电阻或绝缘层。 还提供了碳化硅肖特基二极管和制造碳化硅肖特基二极管的方法，其包括设置在二极管的漂移区域内的碳化硅结壁垒区域。 结阻挡区域包括在二极管的漂移区域中具有第一掺杂浓度的碳化硅的第一区域和漂移区域中的第二碳化硅区域，并且设置在碳化硅的第一区域与肖特基的肖特基接触之间 二极管。 第二区域与碳化硅的第一区域和肖特基接触部接触。 碳化硅的第二区域具有小于第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US08097919B2

公开(公告)日：2012-01-17

申请号：US12189551

申请日：2008-08-11

申请人： Qingchun Zhang ,  Anant K. Agarwal

发明人： Qingchun Zhang ,  Anant K. Agarwal

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/744 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/8613

摘要： An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P−N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P−N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.

摘要翻译： 电子器件包括在漂移层上具有第一导电类型的漂移层，具有与第一导电类型相反的第二导电类型的缓冲层，并形成与漂移层的P-N结，以及接合端接延伸区 在漂移层中具有邻近P-N结的第二导电类型。 缓冲层包括在连接终端延伸部的掩埋部分上延伸的台阶部分。 还公开了相关方法。

公开(公告)号：US20110084284A1

公开(公告)日：2011-04-14

申请号：US12577929

申请日：2009-10-13

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant K. Agarwal ,  Sarit Dhar

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant K. Agarwal ,  Sarit Dhar

IPC分类号： H01L29/778 ,  H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/04 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7813

摘要： A transistor may include a semiconductor drift layer of a first semiconductor material and a semiconductor channel layer on the semiconductor drift layer. The semiconductor channel layer may include a second semiconductor material different than the first semiconductor material. A semiconductor interconnection layer may be electrically coupled between the semiconductor drift layer and the semiconductor channel layer, and the semiconductor interconnection layer may include a third semiconductor material different than the first and second semiconductor materials. In addition, a control electrode may be provided on the semiconductor channel layer.

摘要翻译： 晶体管可以包括第一半导体材料的半导体漂移层和半导体漂移层上的半导体沟道层。 半导体沟道层可以包括与第一半导体材料不同的第二半导体材料。 半导体互连层可以电耦合在半导体漂移层和半导体沟道层之间，并且半导体互连层可以包括不同于第一和第二半导体材料的第三半导体材料。 此外，可以在半导体沟道层上设置控制电极。

公开(公告)号：US20100301929A1

公开(公告)日：2010-12-02

申请号：US12610582

申请日：2009-11-02

申请人： Qingchun Zhang ,  James Theodore Richmond ,  Anant K. Agarwal ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  James Theodore Richmond ,  Anant K. Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L25/00 ,  H01L29/24

CPC分类号： H01L29/7302 ,  H01L21/8213 ,  H01L25/072 ,  H01L25/18 ,  H01L27/0605 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/739 ,  H01L29/7803 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/48137 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

摘要翻译： 半导体开关器件包括宽带隙功率晶体管，与功率晶体管并联耦合的宽带隙浪涌电流晶体管，以及配置为驱动浪涌电流晶体管的宽手持式驱动晶体管。 当功率晶体管的漏极 - 源极电压处于第一电压范围内时，半导体开关器件的大部分导通状态输出电流流过功率晶体管的沟道，该范围可以例如对应于漏极 在正常运行期间预期的电源电压。 相比之下，半导体开关器件被进一步配置成使得在导通状态下，当功率晶体管的漏 - 源电压在一秒内时，输出电流流过功率晶体管的浪涌电流晶体管和沟道， 电压范围

公开(公告)号：US07345310B2

公开(公告)日：2008-03-18

申请号：US11315672

申请日：2005-12-22

申请人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Craig Capell

发明人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Craig Capell

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/1004 ,  H01L29/7325

摘要： A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base layer. An epitaxial silicon carbide passivation layer of the first conductivity type is provided on at least a portion of the epitaxial silicon carbide base layer outside the silicon carbide emitter mesa. The epitaxial silicon carbide passivation layer can be configured to fully deplete at zero device bias. Related fabrication methods also are disclosed.

摘要翻译： 双极结型晶体管（BJT）包括第一导电类型的碳化硅（SiC）集电极层，在碳化硅集电极层上的第二导电类型的外延碳化硅基底层和第一导电类型的外延碳化硅发射极台面 在外延碳化硅基底层上。 第一导电类型的外延碳化硅钝化层设置在碳化硅发射极台面外部的外延碳化硅基底层的至少一部分上。 外延碳化硅钝化层可以被配置为在零器件偏置下完全耗尽。 还公开了相关的制造方法。

公开(公告)号：US07304334B2

公开(公告)日：2007-12-04

申请号：US11229474

申请日：2005-09-16

申请人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  Edward Harold Hurt

发明人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  Edward Harold Hurt

IPC分类号： H01L29/739 ,  H01L31/00

CPC分类号： H01L29/66068 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/732

摘要： Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.

公开(公告)号：US07026650B2

公开(公告)日：2006-04-11

申请号：US10731860

申请日：2003-12-09

申请人： Sei-Hyung Ryu ,  Anant K. Agarwal

发明人： Sei-Hyung Ryu ,  Anant K. Agarwal

IPC分类号： H01L31/312

CPC分类号： H01L29/1608 ,  H01L29/0619

摘要： Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.

摘要翻译： 用于碳化硅器件的边缘终端在碳化硅层中具有与碳化硅基半导体结相邻并间隔开的多个同心浮动保护环。 在浮动保护环上设置绝缘层，例如氧化物，并且在浮动保护环之间提供碳化硅表面电荷补偿区，并且与绝缘层相邻。 还提供了制造这种边缘终止的方法。

公开(公告)号：US06329675B2

公开(公告)日：2001-12-11

申请号：US09788689

申请日：2001-02-19

申请人： Ranbir Singh ,  Anant K. Agarwal ,  Sei-Hyung Ryu

发明人： Ranbir Singh ,  Anant K. Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L310312

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/732

摘要： A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface. A portion of the second layer below the exposed portion of the horizontal surface is then doped with a dopant of the first conductivity type to create a doped well region in the second layer which is spaced from the side wall by a distance defined by the thickness of the dielectric layer. Resulting devices are likewise disclosed.

摘要翻译： 一种在半导体结构中制造自对准双极结型晶体管的方法，其具有通常具有第一导电类型的第一碳化硅层和通常具有与第一导电类型相反的第二导电类型的第二碳化硅层。 该方法包括在第二碳化硅层中形成柱，柱具有侧壁并在第二层上限定相邻的水平表面，在第二半导体层上形成具有预定厚度的介电层，包括侧壁和 水平面。 在形成电介质层之后，邻近侧壁的水平表面的一部分上的电介质层被各向异性地蚀刻，同时电介质层的至少一部分保留在侧壁上，从而暴露出水平表面的一部分。 然后在水平表面的暴露部分下方的第二层的一部分掺杂有第一导电类型的掺杂剂，以在第二层中产生掺杂阱区，该掺杂阱区与侧壁间隔一定距离，该距离由 电介质层。 同样公开了所得到的装置。