公开(公告)号：US20060216875A1

公开(公告)日：2006-09-28

申请号：US11389212

申请日：2006-03-27

申请人： Takayuki Ito ,  Kouji Matsuo ,  Naoki Tamaoki ,  Yoshinori Honguh ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kouji Matsuo ,  Naoki Tamaoki ,  Yoshinori Honguh ,  Kyoichi Suguro

IPC分类号： H01L21/84

CPC分类号： H01L21/324 ,  H01L21/268 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for annealing a semiconductor substrate by light irradiation, includes depositing a translucent film with a predetermined thickness on a semiconductor substrate. The translucent film has a refractive index that is smaller than that of the semiconductor substrate. The thickness is defined by a peak wavelength of the light and the refractive index of the translucent film. The semiconductor substrate is heated in a temperature range of about 300° C. to about 600° C. A surface of the semiconductor substrate is heated with the light which has a pulse width of about 0.1 ms to about 100 ms.

摘要翻译： 通过光照射对半导体衬底进行退火的方法包括在半导体衬底上沉积预定厚度的半透明膜。 半透明膜的折射率小于半导体基板的折射率。 厚度由光的峰值波长和半透明膜的折射率决定。 将半导体衬底在约300℃至约600℃的温度范围内加热。用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面。

公开(公告)号：US07060581B2

公开(公告)日：2006-06-13

申请号：US10960140

申请日：2004-10-08

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/336

CPC分类号： H01L21/823892 ,  H01L21/823807

摘要： A method for manufacturing a semiconductor device, includes forming a first impurity implanted layer in a semiconductor substrate by selectively implanting ions of a first impurity. A dummy pattern is formed on a surface of the semiconductor substrate above the first impurity implanted layer. A second impurity implanted layer is formed in the semiconductor substrate by implanting ions of a second impurity. An interlevel insulating film is buried on the surface of the semiconductor substrate so as to planarize at the level of the dummy pattern. Ions of the first and second impurities are activated by irradiating the semiconductor substrate with a pulsed light at a pulse width of 0.1 ms to 100 ms. An opening is formed by selectively removing the dummy pattern. A gate insulating film and a gate electrode are formed on the exposed surface of the semiconductor substrate.

摘要翻译： 一种半导体器件的制造方法，包括通过选择性地注入第一杂质的离子，在半导体衬底中形成第一杂质注入层。 在第一杂质注入层上方的半导体衬底的表面上形成虚设图形。 通过注入第二杂质的离子，在半导体衬底中形成第二杂质注入层。 在半导体衬底的表面上埋设层间绝缘膜，以在虚拟图案的水平面上平坦化。 通过以0.1ms至100ms的脉冲宽度的脉冲光照射半导体衬底来激活第一和第二杂质的离子。 通过选择性地去除虚拟图案形成开口。 在半导体衬底的暴露表面上形成栅极绝缘膜和栅电极。

公开(公告)号：US07045458B2

公开(公告)日：2006-05-16

申请号：US10924909

申请日：2004-08-25

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/44

CPC分类号： H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor comprises a substrate including a single crystal semiconductor region, and a pattern including a line pattern provided on the substrate, the line pattern having a longitudinal direction differing from a crystal orientation of the single crystal semiconductor region.

摘要翻译： 半导体包括包括单晶半导体区域的衬底和包括设置在衬底上的线图案的图案，该线图案具有与单晶半导体区域的晶体取向不同的纵向方向。

公开(公告)号：US20050202656A1

公开(公告)日：2005-09-15

申请号：US11052861

申请日：2005-02-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6659

摘要： A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

摘要翻译： 一种半导体器件的制造方法，所述方法包括将杂质离子注入到硅层中，并将脉冲宽度为100毫秒或更短的脉冲光和0.3毫秒或更长的上升时间照射到硅层上，从而激活杂质离子 。 上升时间被定义为脉冲光开始上升的瞬间与脉冲光达到峰值能量的瞬间之间的前沿的时间间隔。

公开(公告)号：US06770519B2

公开(公告)日：2004-08-03

申请号：US10263273

申请日：2002-10-03

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21336

CPC分类号： H01L21/324 ,  H01L21/2686 ,  H01L29/6659

摘要： A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the gate electrode and in the surface layer of the semiconductor substrate adjacent to or separate from the gate electrode, performing a first heat treatment, and performing a second heat treatment. The first heat treatment performs heat treatment at a temperature that diffuses the impurity implanted mainly in the gate electrode and controls the diffusion of the impurity implanted in the surface layer of the semiconductor substrate. The second heat treatment performs heat treatment at a higher temperature and for a shorter time than the first heat treatment, and at a temperature that activates the impurity implanted in the semiconductor substrate.

公开(公告)号：US07279405B2

公开(公告)日：2007-10-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。

公开(公告)号：US20070215918A1

公开(公告)日：2007-09-20

申请号：US11704924

申请日：2007-02-12

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US07157340B2

公开(公告)日：2007-01-02

申请号：US11052861

申请日：2005-02-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/332

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6659

摘要： A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

摘要翻译： 一种半导体器件的制造方法，所述方法包括将杂质离子注入到硅层中，并将脉冲宽度为100毫秒或更短的脉冲光和0.3毫秒或更长的上升时间照射到硅层上，从而激活杂质离子 。 上升时间被定义为脉冲光开始上升的瞬间与脉冲光达到峰值能量的瞬间之间的前沿的时间间隔。

公开(公告)号：US07122448B2

公开(公告)日：2006-10-17

申请号：US10926306

申请日：2004-08-26

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/301 ,  H01L21/326

CPC分类号： H01L21/67115 ,  H01L21/26513 ,  H01L21/324

摘要： An annealing apparatus, includes a substrate stage placing a semiconductor substrate; a light source facing the substrate stage, configured to irradiate a pulsed light at a pulse width of approximately 0.1 ms to 100 ms on a surface of the semiconductor substrate; and a mask configured to selectively reduce intensity of the light transmitting a peripheral region along an outer edge of the semiconductor substrate, so as to define an irradiation region by the peripheral region.

摘要翻译： 退火设备包括：放置半导体衬底的衬底台; 面对所述衬底台的光源，被配置为在所述半导体衬底的表面上照射约0.1ms至100ms的脉冲宽度的脉冲光; 以及掩模，其被配置为选择性地降低沿着半导体衬底的外边缘传输周边区域的光的强度，以便通过周边区域限定照射区域。

公开(公告)号：US20050227463A1

公开(公告)日：2005-10-13

申请号：US11097259

申请日：2005-04-04

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

摘要翻译： 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。