公开(公告)号：US07306996B2

公开(公告)日：2007-12-11

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US07297584B2

公开(公告)日：2007-11-20

申请号：US11246471

申请日：2005-10-07

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US20070155165A1

公开(公告)日：2007-07-05

申请号：US11323328

申请日：2005-12-30

申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，用于形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

公开(公告)号：US20060270204A1

公开(公告)日：2006-11-30

申请号：US11498195

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US06864132B2

公开(公告)日：2005-03-08

申请号：US10373005

申请日：2003-02-24

申请人： Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

发明人： Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234

CPC分类号： H01L29/518 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28247

摘要： Integrated circuit gates are fabricated by forming an insulated gate on an integrated circuit substrate, wherein the insulated gate includes a gate oxide on the integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The insulated gate is pretreated with hydrogen and nitrogen gasses. The polysilicon sidewalls are then oxidized. The pretreating in hydrogen and nitrogen gasses prior to oxidizing can reduce growth in thickness of the gate oxide during the oxidizing and/or can reduce formation of whiskers on the metal pattern, compared to absence of the pretreatment.

摘要翻译： 通过在集成电路基板上形成绝缘栅极来制造集成电路栅极，其中绝缘栅极包括在集成电路基板上的栅极氧化物，在栅极氧化物上包括多晶硅侧壁的多晶硅图案，以及多晶硅图案上的金属图案 。 绝缘栅极用氢气和氮气预处理。 然后将多晶硅侧壁氧化。 在氧化之前在氢气和氮气中预处理可以减少在氧化期间栅极氧化物的厚度增长和/或可以减少与不进行预处理相比在金属图案上形成晶须。

公开(公告)号：US07781322B2

公开(公告)日：2010-08-24

申请号：US10726638

申请日：2003-12-04

申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

IPC分类号： H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4941 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.

摘要翻译： 提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分 合金化金属如钽，并且显示减少的结块并延缓NiSi和NiSi2之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。 如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

公开(公告)号：US07544996B2

公开(公告)日：2009-06-09

申请号：US11498195

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US07435673B2

公开(公告)日：2008-10-14

申请号：US11237987

申请日：2005-09-28

申请人： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

发明人： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

摘要： Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

摘要翻译： 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。

公开(公告)号：US20070072406A1

公开(公告)日：2007-03-29

申请号：US11237987

申请日：2005-09-28

申请人： Kyoung Lee ,  Ja-Hum Ku ,  Duk Hong ,  Wan Park

发明人： Kyoung Lee ,  Ja-Hum Ku ,  Duk Hong ,  Wan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

摘要： Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

摘要翻译： 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。

公开(公告)号：US07109104B2

公开(公告)日：2006-09-19

申请号：US10665122

申请日：2003-09-22

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).