公开(公告)号：US20200046988A1

公开(公告)日：2020-02-13

申请号：US16537025

申请日：2019-08-09

Applicant: Medtronic, Inc.

Inventor： Jeffrey D. Wilkinson ,  Darrell J. Swenson

IPC: A61N1/39 ,  A61B5/11 ,  A61B5/08

Abstract: In some examples, a method for controlling delivery of cardiac therapy and cardiac sensing by a medical device system including electrodes for delivering the cardiac therapy may include storing, in a memory of the medical device system, a respective value for each of a plurality of cardiac therapy and/or sensing parameters and, in association with each of a plurality of heart position states, a respective modification of at least one of the cardiac therapy and/or sensing parameters. Such a method also may include determining a current one of the plurality of heart position states of the patient, modifying the at least one cardiac therapy and/or sensing parameter value according to the modification associated with the current heart position state, and controlling the delivery of the cardiac therapy and/or cardiac sensing according to the modified at least one cardiac therapy and/or sensing parameter value.

公开(公告)号：US09607708B2

公开(公告)日：2017-03-28

申请号：US13665409

申请日：2012-10-31

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/30 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C7/14 ,  G11C11/00 ,  G11C17/12 ,  G11C29/50

CPC classification number: G11C16/30 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227 ,  G11C11/005 ,  G11C16/26 ,  G11C16/28 ,  G11C17/12 ,  G11C29/50 ,  G11C29/50004

Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

公开(公告)号：US09053791B2

公开(公告)日：2015-06-09

申请号：US13665461

申请日：2012-10-31

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/10 ,  G11C16/04 ,  G11C17/12

CPC classification number: G11C16/04 ,  G11C17/12 ,  G11C2216/26

Abstract: Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

Abstract translation: 用于存储多个数据位的存储器阵列。 存储器阵列具有闪存单元，ROM存储单元寻址电路。 寻址电路可操作地耦合到多个闪速存储器单元和多个ROM存储器单元，寻址电路被配置为寻址多个闪存单元和多个ROM存储单元。