公开(公告)号：US20140282336A1

公开(公告)日：2014-09-18

申请号：US13802895

申请日：2013-03-14

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Melvin P. Roberts

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/62

Abstract: Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.

Abstract translation: 描述了用于为包括时钟树网络的集成电路产生时序约束的技术。 这些技术可以与时钟树合成工具相关联，时钟树合成工具接收集成电路的设计并生成包括集成电路的多个时钟元件的时钟树网络。 约束可以作为数据信号从耦合到接收时钟部件的发送时钟元件传播的持续时间的函数而产生。

公开(公告)号：US20130238840A1

公开(公告)日：2013-09-12

申请号：US13663099

申请日：2012-10-29

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Charles R. Gordon ,  Paul R. Solheim ,  Jerry D. Reiland ,  Robert D. Musto ,  Duane R. Bigelow

IPC: G06F12/00

CPC classification number: G11C11/005 ,  G06F3/0601 ,  G06F3/0646 ,  G06F3/0668 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0868 ,  G06F13/387 ,  G06F13/42 ,  G06F13/4234 ,  G11C16/10

Abstract: Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

Abstract translation: 用于存储数据的存储器阵列，系统和方法。 存储器阵列具有闪存阵列，耦合到闪存并被配置为接收数据的随机存取存储器阵列，存储器管理模块和数据总线。 存储器管理模块耦合到随机存取存储器阵列和闪速存储器阵列，存储器管理模块被配置为将存储在随机存取存储器阵列中的数据的至少一部分传送到闪存阵列。 数据总线耦合到闪速存储器阵列并且被配置为从闪速存储器阵列输出原始存储在随机存取存储器阵列中的数据的至少一部分。

公开(公告)号：US20130235663A1

公开(公告)日：2013-09-12

申请号：US13665409

申请日：2012-10-31

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227 ,  G11C11/005 ,  G11C16/26 ,  G11C16/28 ,  G11C17/12 ,  G11C29/50 ,  G11C29/50004

Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

Abstract translation: 电可擦除闪存和方法。 存储器具有数据存储元件和电压感测电路。 数据存储元件被配置为存储数据位，每个数据位具有数据状态。 电压感测电路选择性地耦合到单个数据位，并且被配置为利用偏置电流和偏置电阻中的至少一个偏置数据位，并读取多个数据位中的各个数据位的数据状态。

公开(公告)号：US10096350B2

公开(公告)日：2018-10-09

申请号：US13663099

申请日：2012-10-29

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Charles R. Gordon ,  Paul R. Solheim ,  Jerry D. Reiland ,  Robert D. Musto ,  Duane R. Bigelow

IPC: G06F12/00 ,  G11C11/00 ,  G11C16/10 ,  G06F13/42 ,  G06F3/06 ,  G06F13/38 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/06

Abstract: Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

公开(公告)号：US20140276664A1

公开(公告)日：2014-09-18

申请号：US13802877

申请日：2013-03-14

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Melvin P. Roberts

IPC: A61M5/168 ,  H03K3/012

CPC classification number: H03K5/1504 ,  A61M5/14276 ,  A61M2205/8212 ,  G06F1/10

Abstract: An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.

Abstract translation: 集成电路包括时钟树网络，其将时钟信号分配给集成电路的多个时钟元件。 时钟树网络包括时钟线，每个时钟线包括时钟树延迟元件，时钟树延迟元件提供被提供给单个时钟元件的修改时钟信号。 在多个时钟元件中，一个或多个时钟元件向另一个或多个时钟元件提供数据信号。 一个或多个时钟元件被配置为具有相对于接收时钟部件的经修改的时钟信号的传输持续时间更长的数据信号的传输持续时间。

公开(公告)号：US20130235672A1

公开(公告)日：2013-09-12

申请号：US13665461

申请日：2012-10-31

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C17/12 ,  G11C2216/26

Abstract: Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

Abstract translation: 用于存储多个数据位的存储器阵列。 存储器阵列具有闪存单元，ROM存储单元寻址电路。 寻址电路可操作地耦合到多个闪速存储器单元和多个ROM存储器单元，寻址电路被配置为寻址多个闪存单元和多个ROM存储单元。

公开(公告)号：US20130182523A1

公开(公告)日：2013-07-18

申请号：US13791827

申请日：2013-03-08

Applicant: STMicroelectronics S.A. ,  Medtronic, Inc. ,  STMicroelectronics Inc.

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约高SRAM和低SRAM电源电压之间的电压。

公开(公告)号：US09660626B2

公开(公告)日：2017-05-23

申请号：US13802877

申请日：2013-03-14

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Melvin P. Roberts

IPC: H03K3/00 ,  H03K5/15 ,  G06F1/10 ,  A61M5/142

CPC classification number: H03K5/1504 ,  A61M5/14276 ,  A61M2205/8212 ,  G06F1/10

Abstract: An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.

公开(公告)号：US09378805B2

公开(公告)日：2016-06-28

申请号：US13663939

申请日：2012-10-30

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Brandon P. Scott ,  Larry E. Tyler

IPC: G11C11/417

CPC classification number: G11C11/417

Abstract: Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.

Abstract translation: 具有多个存储器单元的随机存取存储器，所述多个存储器单元中的每一个具有存储元件和第一电特性，所述第一电特性至少部分地基于温度和偏置电路而变化，所述偏置电路可操作地耦合到所述多个存储器单元中的至少一个 所述偏置电路被配置为产生所述多个存储器单元中的所述至少一个存储器单元的偏置电压。 偏置电路具有至少部分地基于温度变化的第二电特性。 在预定温度范围内，第一电特性与第二电特性近似成比例，预定温度范围大于零。 多个存储单元中的每一个上的偏置电压几乎与预定温度范围内的第一电特性的变化成比例。

公开(公告)号：US08654574B2

公开(公告)日：2014-02-18

申请号：US13791827

申请日：2013-03-08

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics SA ,  Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  François Jacquet

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。