Abstract:
Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.
Abstract:
Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.
Abstract:
Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.
Abstract:
Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.
Abstract:
An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.
Abstract:
Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.
Abstract:
An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
Abstract:
An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.
Abstract:
Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.
Abstract:
An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.