公开(公告)号：US20130170287A1

公开(公告)日：2013-07-04

申请号：US13663939

申请日：2012-10-30

Applicant: MEDTRONIC, INC.

Inventor： Kevin K. Walsh ,  Brandon P. Scott ,  Larry E. Tyler

IPC: G11C11/00

CPC classification number: G11C11/417

Abstract: Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.

Abstract translation: 具有多个存储器单元的随机存取存储器，所述多个存储器单元中的每一个具有存储元件和第一电特性，所述第一电特性至少部分地基于温度和偏置电路而变化，所述偏置电路可操作地耦合到所述多个存储器单元中的至少一个 所述偏置电路被配置为产生所述多个存储器单元中的所述至少一个存储器单元的偏置电压。 偏置电路具有至少部分地基于温度变化的第二电特性。 在预定温度范围内，第一电特性与第二电特性近似成比例，预定温度范围大于零。 多个存储单元中的每一个上的偏置电压几乎与预定温度范围内的第一电特性的变化成比例。

公开(公告)号：US09607708B2

公开(公告)日：2017-03-28

申请号：US13665409

申请日：2012-10-31

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/30 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C7/14 ,  G11C11/00 ,  G11C17/12 ,  G11C29/50

CPC classification number: G11C16/30 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227 ,  G11C11/005 ,  G11C16/26 ,  G11C16/28 ,  G11C17/12 ,  G11C29/50 ,  G11C29/50004

Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

公开(公告)号：US09053791B2

公开(公告)日：2015-06-09

申请号：US13665461

申请日：2012-10-31

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul B. Patterson ,  Glen W. Benton ,  Jeffrey D. Wilkinson

IPC: G11C16/10 ,  G11C16/04 ,  G11C17/12

CPC classification number: G11C16/04 ,  G11C17/12 ,  G11C2216/26

Abstract: Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

Abstract translation: 用于存储多个数据位的存储器阵列。 存储器阵列具有闪存单元，ROM存储单元寻址电路。 寻址电路可操作地耦合到多个闪速存储器单元和多个ROM存储器单元，寻址电路被配置为寻址多个闪存单元和多个ROM存储单元。

公开(公告)号：US08839178B1

公开(公告)日：2014-09-16

申请号：US13802895

申请日：2013-03-14

Applicant: Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Melvin P. Roberts

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/62

Abstract: Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.

Abstract translation: 描述了用于为包括时钟树网络的集成电路产生时序约束的技术。 这些技术可以与时钟树合成工具相关联，时钟树合成工具接收集成电路的设计并生成包括集成电路的多个时钟元件的时钟树网络。 约束可以作为数据信号从耦合到接收时钟部件的发送时钟元件传播的持续时间的函数而产生。