公开(公告)号：US11762785B2

公开(公告)日：2023-09-19

申请号：US17306033

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Ilan Pardo ,  Yamin Friedman ,  Michael Cotsford ,  Mark Rosenbluth ,  Hillel Chapman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/0811 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F12/0811 ,  G06F13/382 ,  G06F13/4221 ,  G06F15/7807 ,  G06F2213/0026

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

公开(公告)号：US10528519B2

公开(公告)日：2020-01-07

申请号：US15584327

申请日：2017-05-02

Applicant: Mellanox Technologies Ltd.

Inventor： Mark Rosenbluth

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F15/80

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.