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公开(公告)号：US12216604B2
公开(公告)日：2025-02-04
申请号：US17958111
申请日：2022-09-30
Applicant: Mellanox Technologies, Ltd.
Inventor： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.
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公开(公告)号：US20240111702A1
公开(公告)日：2024-04-04
申请号：US17958111
申请日：2022-09-30
Applicant: Mellanox Technologies, Ltd.
Inventor： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC classification number: G06F13/4045 , G06F13/24
Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.
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公开(公告)号：US20240231967A1
公开(公告)日：2024-07-11
申请号：US18094182
申请日：2023-01-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Diane Orf , Mark Rosenbluth , Michael Cotsford , Rui Xu , Shreya Tekade
Abstract: An integrated circuit includes a set of functional units having at least a first functional unit and a second functional unit. The first functional unit includes first processing circuitry and a first circuit coupled to the first processing circuitry to receive a message from the second functional unit of the set of functional units. The first circuit is further to delay the message for the first processing circuitry for a predetermined duration, where the predetermined duration is based in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.
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公开(公告)号：US20240111694A1
公开(公告)日：2024-04-04
申请号：US17958229
申请日：2022-09-30
Applicant: Mellanox Technologies, Ltd.
Inventor： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC classification number: G06F13/1668 , G06F13/4221 , G06F2213/0026
Abstract: A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.
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公开(公告)号：US20220350756A1
公开(公告)日：2022-11-03
申请号：US17306033
申请日：2021-05-03
Applicant: Mellanox Technologies LTD.
Inventor： Idan Burstein , Ilan Pardo , Yamin Friedman , Michael Cotsford , Mark Rosenbluth , Hillel Chapman
Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.
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Patent Agency Ranking
公开(公告)号：US20180322057A1
公开(公告)日：2018-11-08
申请号：US15584327
申请日：2017-05-02
Applicant: Mellanox Technologies Ltd.
Inventor： Mark Rosenbluth
IPC: G06F12/0817 , G06F15/80 , G06F12/0815 , G06F12/084
CPC classification number: G06F15/80 , G06F12/0813 , G06F12/0831 , G06F15/76 , G06F2212/1016
Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.
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公开(公告)号：US20250013585A1
公开(公告)日：2025-01-09
申请号：US18884934
申请日：2024-09-13
Applicant: Mellanox Technologies, Ltd.
Inventor： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
Abstract: A system includes tiles arranged in a configurable topology. A first tile includes memory and one or more processing devices to: receive a first message including a coordinate identifier of a target tile, the coordinate identifier reflecting a location of the target tile; update a configuration value associated with the target tile based on the coordinate identifier, and transmit a second message to the target tile based on the configuration value.
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公开(公告)号：US12111779B2
公开(公告)日：2024-10-08
申请号：US17958229
申请日：2022-09-30
Applicant: Mellanox Technologies, Ltd.
Inventor： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC classification number: G06F13/1668 , G06F13/4221 , G06F2213/0026
Abstract: A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.
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公开(公告)号：US11762785B2
公开(公告)日：2023-09-19
申请号：US17306033
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Idan Burstein , Ilan Pardo , Yamin Friedman , Michael Cotsford , Mark Rosenbluth , Hillel Chapman
CPC classification number: G06F13/1668 , G06F12/0246 , G06F12/0811 , G06F13/382 , G06F13/4221 , G06F15/7807 , G06F2213/0026
Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.
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公开(公告)号：US10528519B2
公开(公告)日：2020-01-07
申请号：US15584327
申请日：2017-05-02
Applicant: Mellanox Technologies Ltd.
Inventor： Mark Rosenbluth
Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.
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