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    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF DATA ERASE IN THE SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF DATA ERASE IN THE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件，半导体器件和半导体存储器件中的数据擦除方法

    公开(公告)号：US20110182125A1

    公开(公告)日：2011-07-28

    申请号：US12883474

    申请日：2010-09-16

    申请人： Mikihiko ITOH ,  Takeshi Nakano ,  Michio Nakagawa

    发明人： Mikihiko ITOH ,  Takeshi Nakano ,  Michio Nakagawa

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/30

    摘要： A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.

    摘要翻译： 根据实施例的半导体存储器件包括存储单元阵列和擦除电压产生电路。 存储单元阵列被配置为非易失性存储单元的布置。 擦除电压产生电路被配置为产生用于执行存储单元阵列的数据擦除的擦除电压。 擦除电压产生电路被配置为在擦除电压被施加到多个擦除周期中的存储单元阵列的选定区域的数据擦除模式中，将擦除电压的初始阶段的擦除电压的上升波形 多个擦除周期比随后的周期中的擦除电压的上升波形不那么陡。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    12.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20100080063A1

    公开(公告)日：2010-04-01

    申请号：US12504201

    申请日：2009-07-16

    申请人： Michio Nakagawa

    发明人： Michio Nakagawa

    IPC分类号： G11C16/04 ,  G11C5/14

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483

    摘要： A nonvolatile semiconductor memory device includes a memory cell group, transfer transistor, and switching circuit. The memory cell group has a plurality of memory cells each including a floating gate and control gate, and the current paths of the plurality of memory cells are connected in series. The transfer transistor transfers a write voltage to at least one memory cell in the memory cell group. The switching circuit applies a voltage to the gate of the transfer transistor. In a write operation, when a first voltage higher than a power supply voltage and lower than the write voltage is applied to the control gate of an unselected memory cell, the switching circuit applies an intermediate voltage higher than the first voltage and equal to or lower than the write voltage to the gate of the transfer transistor.

    摘要翻译： 非易失性半导体存储器件包括存储单元组，转移晶体管和开关电路。 存储单元组具有多个存储单元，每个存储单元包括浮置栅极和控制栅极，并且多个存储单元的电流路径串联连接。 传输晶体管将写入电压传送到存储器单元组中的至少一个存储单元。 开关电路向转移晶体管的栅极施加电压。 在写入操作中，当高于电源电压并低于写入电压的第一电压被施加到未选择存储单元的控制栅极时，开关电路施加高于第一电压并等于或等于 比对转移晶体管的栅极的写入电压。