公开(公告)号：US20230043733A1

公开(公告)日：2023-02-09

申请号：US17395695

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20220413714A1

公开(公告)日：2022-12-29

申请号：US17357436

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Jianmin Huang ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode.

公开(公告)号：US20220350521A1

公开(公告)日：2022-11-03

申请号：US17244290

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Ting Luo ,  Jianmin Huang

IPC: G06F3/06

Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

公开(公告)号：US20220261313A1

公开(公告)日：2022-08-18

申请号：US17734444

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Lakshmi Kalpana Vakati ,  Harish R. Singidi

IPC: G06F11/10 ,  G06F3/06

Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

公开(公告)号：US20210390014A1

公开(公告)日：2021-12-16

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/0882 ,  G06F11/07 ,  G06F12/02

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210255960A1

公开(公告)日：2021-08-19

申请号：US16998631

申请日：2020-08-20

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jianmin Huang ,  Tomoko Ogura Iwasaki ,  Kishore Kumar Muchherla ,  Peter Sean Feeley

IPC: G06F12/0882 ,  G06F12/0811 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/00

Abstract: Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).

公开(公告)号：US20210149564A1

公开(公告)日：2021-05-20

申请号：US16685300

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Ankit Vinod Vashi ,  Xiangang Luo ,  Jianmin Huang

IPC: G06F3/06

Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.

公开(公告)号：US20210124519A1

公开(公告)日：2021-04-29

申请号：US17140785

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jianmin Huang ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G06F12/02 ,  G06F1/3234

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

公开(公告)号：US20210064495A1

公开(公告)日：2021-03-04

申请号：US16560560

申请日：2019-09-04

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/30 ,  G06F11/07 ,  G06F12/14 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the PIE cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

公开(公告)号：US20210057018A1

公开(公告)日：2021-02-25

申请号：US16947795

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

IPC: G11C11/408 ,  G11C11/4074 ,  G06F12/02

Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.