公开(公告)号：US20210342262A1

公开(公告)日：2021-11-04

申请号：US17375478

申请日：2021-07-14

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale

IPC分类号： G06F12/02 ,  G06F12/0897 ,  G06F12/128

摘要： A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.

公开(公告)号：US11075163B2

公开(公告)日：2021-07-27

申请号：US14810044

申请日：2015-07-27

申请人： Micron Technology, Inc.

发明人： Koji Sakui ,  Peter Sean Feeley ,  Akira Goda

IPC分类号： G11C16/04 ,  H01L23/528 ,  G11C11/56 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L23/535 ,  H01L29/49

摘要： Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

公开(公告)号：US10691377B2

公开(公告)日：2020-06-23

申请号：US16138334

申请日：2018-09-21

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, Jr. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC分类号： G06F12/00 ,  G06F3/06 ,  G11C16/34

摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US20200160894A1

公开(公告)日：2020-05-21

申请号：US16749481

申请日：2020-01-22

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Reddy Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC分类号： G11C7/10 ,  G11C29/02 ,  G11C8/10

摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10579307B2

公开(公告)日：2020-03-03

申请号：US16566545

申请日：2019-09-10

申请人： Micron Technology, Inc.

发明人： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Sampath Ratnam ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C16/08

摘要： Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

公开(公告)号：US20190066792A1

公开(公告)日：2019-02-28

申请号：US15690920

申请日：2017-08-30

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Thomson ,  Harish Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC分类号： G11C16/10 ,  G11C16/22

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/22 ,  G11C16/28 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

摘要： Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US09093152B2

公开(公告)日：2015-07-28

申请号：US13661498

申请日：2012-10-26

申请人： Micron Technology, Inc.

发明人： Koji Sakui ,  Peter Sean Feeley ,  Akira Goda

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L23/528 ,  G11C11/5671 ,  G11C16/0483 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/535 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4975 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

摘要翻译： 公开了装置和方法，包括具有耦合到公共源的存储器单元的垂直串行的装置和与每行垂直串相关联的多个数据线的装置。 与行相关联的每个数据行被耦合到行中的至少一个垂直字符串。 描述附加的装置和方法。

公开(公告)号：US20140313839A1

公开(公告)日：2014-10-23

申请号：US13868548

申请日：2013-04-23

申请人： MICRON TECHNOLOGY, INC.

发明人： Koji Sakui ,  Peter Sean Feeley

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C7/106 ,  G11C7/12 ,  G11C7/22 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/108

摘要： Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.

摘要翻译： 一些实施例包括用于在设备的存储器操作期间激活与耦合到不同组的存储器单元的访问线相关联的信号的装置和方法，以及用于在存储器操作的不同时间间隔期间感测设备的数据线以确定值 存储在存储单元中的信息。 每个数据线可以耦合到每组存储器单元的相应存储单元。 在这样的装置和方法中的至少一个中，施加到访问线路的信号可以在存储器操作期间保持激活。

公开(公告)号：US08713385B2

公开(公告)日：2014-04-29

申请号：US13741148

申请日：2013-01-14

申请人： Micron Technology, Inc.

发明人： William Henry Radke ,  Peter Sean Feeley ,  Siamack Nemazie

IPC分类号： G11C29/00

CPC分类号： G06F11/006 ,  G06F11/106

摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。

公开(公告)号：US20210257008A1

公开(公告)日：2021-08-19

申请号：US17175999

申请日：2021-02-15

申请人： Micron Technology, Inc.

发明人： Koji Sakui ,  Peter Sean Feeley

IPC分类号： G11C7/06 ,  G11C16/04 ,  G11C16/26 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22

摘要： Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.