公开(公告)号：US20240272831A1

公开(公告)日：2024-08-15

申请号：US18583540

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20240070284A1

公开(公告)日：2024-02-29

申请号：US18237247

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Niccolò Izzo ,  Angelo Alberto Rovelli ,  Danilo Caraccio ,  Federica Cresci ,  Craig A. Jones

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F2221/033

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified, an open sub-system can be placed into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system can be subsequently placed into a resume state to further perform the boot procedure when the boot firmware is verified. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified unless the open sub-system is placed into the resume state again.

公开(公告)号：US20240070283A1

公开(公告)日：2024-02-29

申请号：US18237229

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Niccolò Izzo ,  Angelo Alberto Rovelli ,  Danilo Caraccio ,  Federica Cresci ,  Craig A. Jones

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.

公开(公告)号：US20220155997A1

公开(公告)日：2022-05-19

申请号：US16951985

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US12197631B2

公开(公告)日：2025-01-14

申请号：US17562916

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/10 ,  G06F21/55 ,  G06F21/60 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US12068050B2

公开(公告)日：2024-08-20

申请号：US17831329

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Craig A. Jones

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/52 ,  G11C29/021 ,  G11C29/023

Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

公开(公告)号：US20230395181A1

公开(公告)日：2023-12-07

申请号：US17831329

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Craig A. Jones

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/023 ,  G11C29/021

Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

公开(公告)号：US20230394155A1

公开(公告)日：2023-12-07

申请号：US17969916

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Alessandro Orlando ,  Craig A. Jones ,  Federica Cresci ,  Niccolò Izzo ,  Danilo Caraccio

IPC: G06F21/57 ,  G06F8/654 ,  G06F21/60 ,  H04L9/06

CPC classification number: G06F21/572 ,  G06F8/654 ,  G06F2221/033 ,  H04L9/0631 ,  G06F21/602

Abstract: Methods, systems, and devices related to field firmware update (FFU). A first memory of a memory module may receive an encrypted segment of a FW package associated with FFU. A decrypted segment of the FW package may be stored by the first memory. A re-encrypted segment of the FW package may be stored by the first memory. The re-encrypted segment of the FW package may be communicated to a second memory of the memory module.

公开(公告)号：US11544201B2

公开(公告)日：2023-01-03

申请号：US17169042

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Danilo Caraccio ,  Angelo Alberto Rovelli

IPC: G06F12/1027 ,  G06F3/06 ,  G06F9/30 ,  G06F9/455

Abstract: Systems, apparatuses, and methods related to memory tracing in an emulated computing system are described. Static tracepoints can be inserted into a particular function as part of operating the emulated computing system. By executing the function including the static tracepoints as part of a memory access request, the emulated computing system can receive information corresponding to both a virtual address and a physical address in a real computing system in which data corresponding to the memory access request is stored.