GLITCH DETECTION REDUNDANCY
    1.
    发明申请

    公开(公告)号:US20240412805A1

    公开(公告)日:2024-12-12

    申请号:US18808418

    申请日:2024-08-19

    Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

    SECURE BOOT PROCEDURE
    2.
    发明公开

    公开(公告)号:US20240070284A1

    公开(公告)日:2024-02-29

    申请号:US18237247

    申请日:2023-08-23

    CPC classification number: G06F21/575 G06F21/572 G06F2221/033

    Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified, an open sub-system can be placed into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system can be subsequently placed into a resume state to further perform the boot procedure when the boot firmware is verified. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified unless the open sub-system is placed into the resume state again.

    SECURE BOOT PROCEDURE
    3.
    发明公开

    公开(公告)号:US20240070283A1

    公开(公告)日:2024-02-29

    申请号:US18237229

    申请日:2023-08-23

    CPC classification number: G06F21/575 G06F21/572

    Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.

    SECURITY MANAGEMENT OF FERROELECTRIC MEMORY DEVICE

    公开(公告)号:US20250148133A1

    公开(公告)日:2025-05-08

    申请号:US19013585

    申请日:2025-01-08

    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

    GLITCH DETECTION
    5.
    发明公开
    GLITCH DETECTION 审中-公开

    公开(公告)号:US20240185938A1

    公开(公告)日:2024-06-06

    申请号:US18516121

    申请日:2023-11-21

    CPC classification number: G11C29/08 G11C29/023

    Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

    SECURITY MANAGEMENT OF FERROELECTRIC MEMORY DEVICE

    公开(公告)号:US20220207193A1

    公开(公告)日:2022-06-30

    申请号:US17562916

    申请日:2021-12-27

    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

    Security management of ferroelectric memory device

    公开(公告)号:US12197631B2

    公开(公告)日:2025-01-14

    申请号:US17562916

    申请日:2021-12-27

    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

    Glitch detection redundancy
    8.
    发明授权

    公开(公告)号:US12068050B2

    公开(公告)日:2024-08-20

    申请号:US17831329

    申请日:2022-06-02

    CPC classification number: G11C29/52 G11C29/021 G11C29/023

    Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

    GLITCH DETECTION REDUNDANCY
    9.
    发明公开

    公开(公告)号:US20230395181A1

    公开(公告)日:2023-12-07

    申请号:US17831329

    申请日:2022-06-02

    CPC classification number: G11C29/52 G11C29/023 G11C29/021

    Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

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