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11.
公开(公告)号:US20210375670A1
公开(公告)日:2021-12-02
申请号:US17444948
申请日:2021-08-12
Applicant: Micron Technology, Inc.
Inventor: Xiaosong Zhang , Yongjun J. Hu , David A. Kewley , Md Zahid Hossain , Michael J. Irwin , Daniel Billingsley , Suresh Ramarajan , Robert J. Hanson , Biow Hiem Ong , Keen Wah Chow
IPC: H01L21/768
Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
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12.
公开(公告)号:US20210111064A1
公开(公告)日:2021-04-15
申请号:US16599856
申请日:2019-10-11
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , Yongjun Jeff Hu
IPC: H01L21/762 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.
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公开(公告)号:US11552090B2
公开(公告)日:2023-01-10
申请号:US17068470
申请日:2020-10-12
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , John D. Hopkins , Yongjun Jeff Hu , Swapnil Lengade
IPC: H01L27/11582 , H01L27/11556 , G11C16/04 , H01L27/11519 , H01L27/11565 , H01L27/1157 , H01L27/11524
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20220068959A1
公开(公告)日:2022-03-03
申请号:US17068430
申请日:2020-10-12
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , John D. Hopkins , Yongjun Jeff Hu , Swapnil Lengade
IPC: H01L27/11582 , H01L27/11556 , H01L21/311
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20220020763A1
公开(公告)日:2022-01-20
申请号:US16928345
申请日:2020-07-14
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , John D. Hopkins , Yongjun Jeff Hu
IPC: H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
Abstract: A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed.
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公开(公告)号:US20210287989A1
公开(公告)日:2021-09-16
申请号:US16817267
申请日:2020-03-12
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins , Rita J. Klein , Everett A. McTeer , Lifang Xu , Daniel Billingsley , Collin Howder
IPC: H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/768
Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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17.
公开(公告)号:US20210233801A1
公开(公告)日:2021-07-29
申请号:US17228937
申请日:2021-04-13
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , Yongjun Jeff Hu
IPC: H01L21/762 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.
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18.
公开(公告)号:US11011408B2
公开(公告)日:2021-05-18
申请号:US16599856
申请日:2019-10-11
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , Yongjun Jeff Hu
IPC: H01L21/762 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L21/311 , H01L27/11556 , H01L27/11582 , H01L21/3115
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.
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19.
公开(公告)号:US20210057428A1
公开(公告)日:2021-02-25
申请号:US16550238
申请日:2019-08-25
Applicant: Micron Technology, Inc.
Inventor: Yi Hu , Ramey M. Abdelrahaman , Narula Bilik , Daniel Billingsley , Zhenyu Bo , Joan M. Kash , Matthew J. King , Andrew Li , David Neumeyer , Wei Yeeng Ng , Yung K. Pak , Chandra Tiwari , Yiping Wang , Lance Williamson , Xiaosong Zhang
IPC: H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11582
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
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公开(公告)号:US20210050252A1
公开(公告)日:2021-02-18
申请号:US16542507
申请日:2019-08-16
Applicant: Micron Technology, Inc.
Inventor: Xiaosong Zhang , Yongjun J. Hu , David A. Kewley , Md Zahid Hossain , Michael J. Irwin , Daniel Billingsley , Suresh Ramarajan , Robert J. Hanson , Biow Hiem Ong , Keen Wah Chow
IPC: H01L21/768
Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
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