公开(公告)号：US20230267977A1

公开(公告)日：2023-08-24

申请号：US17680006

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1039 ,  G11C7/18

Abstract: Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.

公开(公告)号：US20230112259A1

公开(公告)日：2023-04-13

申请号：US17968593

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: H01L29/02 ,  G11C11/22

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US11605412B2

公开(公告)日：2023-03-14

申请号：US17196650

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

公开(公告)号：US20220415381A1

公开(公告)日：2022-12-29

申请号：US17362280

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06 ,  G05F3/26

Abstract: Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

公开(公告)号：US11482268B2

公开(公告)日：2022-10-25

申请号：US17387327

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408

Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.

公开(公告)号：US11417380B2

公开(公告)日：2022-08-16

申请号：US17072566

申请日：2020-10-16

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/00 ,  G11C14/00

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US20220020417A1

公开(公告)日：2022-01-20

申请号：US17387327

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/4096 ,  G11C11/4091

Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.

公开(公告)号：US11222668B1

公开(公告)日：2022-01-11

申请号：US17004402

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Duane R. Mills ,  Richard E. Fackenthal ,  Yasuko Hattori

IPC: G11C11/22 ,  G11C11/56 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14

Abstract: Methods, systems, and devices for memory cell sensing stress mitigation are described. A memory device may be configured to bias a memory cell to a voltage with a first polarity or a second polarity (e.g., a positive voltage or a negative voltage) during an access operation to level wear experienced by the memory cell during the access operation. For example, during a first read operation, a first pulse with the first polarity (e.g., a negative voltage) may be applied to the memory cell to read out a first logic state stored at the memory cell. During a second read operation, a second pulse with the second polarity (e.g., a positive voltage) may be applied to the memory cell to read out a second logic state stored at the memory cell. The memory device may include a selection component for selecting between the different pulses used for different read operations.

公开(公告)号：US20210335408A1

公开(公告)日：2021-10-28

申请号：US17236741

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

Abstract: Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.

公开(公告)号：US20210312968A1

公开(公告)日：2021-10-07

申请号：US17236734

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes.