公开(公告)号：US11681461B2

公开(公告)日：2023-06-20

申请号：US17532020

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US11656794B2

公开(公告)日：2023-05-23

申请号：US17140839

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

公开(公告)号：US20230051212A1

公开(公告)日：2023-02-16

申请号：US17399406

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David Aaron Palmer ,  Giuseppe Cariello

IPC: G06F12/02 ,  G06F3/06

Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

公开(公告)号：US11550711B2

公开(公告)日：2023-01-10

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US11520524B2

公开(公告)日：2022-12-06

申请号：US17157539

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.

公开(公告)号：US20220358012A1

公开(公告)日：2022-11-10

申请号：US17872462

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/10 ,  H03M13/29

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

公开(公告)号：US11314427B2

公开(公告)日：2022-04-26

申请号：US17000015

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US20210233593A1

公开(公告)日：2021-07-29

申请号：US17232725

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.

公开(公告)号：US20210073121A1

公开(公告)日：2021-03-11

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A a current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US20210065766A1

公开(公告)日：2021-03-04

申请号：US16553358

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C11/409 ,  G06F12/02 ,  G06F3/06 ,  G06F13/16

Abstract: Devices and techniques are disclosed herein to address high latency associated with large-scale un-map or trim commands associated with flash memory. In an example, a method can include receiving a trim command for a partition of a storage system, identifying a record of a partition table of the storage system corresponding to the partition, updating a partition count of the record with a count value of a partition counter of the storage system, and incrementing the partition counter.