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    Memory management for a hierarchical memory system
    12.
    发明授权
    Memory management for a hierarchical memory system 有权

    公开(公告)号：US10831672B2

    公开(公告)日：2020-11-10

    申请号：US16107662

    申请日：2018-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Dean A. Klein

    IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/123 ,  G06F12/1027

    Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

    Systems, devices, and methods for selective communication through an electrical connector
    15.
    发明授权
    Systems, devices, and methods for selective communication through an electrical connector 有权

    公开(公告)号：US09804989B2

    公开(公告)日：2017-10-31

    申请号：US14341262

    申请日：2014-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Dean A. Klein

    IPC: G06F3/00 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4221 ,  G06F13/4022 ,  G06F13/4068

    Abstract: Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from another electronic device. The other electronic device is configured to provide a protocol indicator that indicates a particular communication protocol with which the other electronic device is configured to communicate through an electrical connector of the electronic device. A method includes receiving a protocol indicator from another electronic device through an electrical connector. The protocol indicator indicates a communication protocol. The method also includes communicating with the other electronic device through the electrical connector using the indicated communication protocol.

    GENERATING AND EXECUTING A CONTROL FLOW
    17.
    发明申请
    GENERATING AND EXECUTING A CONTROL FLOW 审中-公开
    生成和执行控制流程

    公开(公告)号：US20160196142A1

    公开(公告)日：2016-07-07

    申请号：US14980024

    申请日：2015-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

    IPC: G06F9/30

    CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

    Abstract translation: 本公开的示例提供与生成和执行控制流有关的装置和方法。 示例性设备可以包括被配置为生成控制流指令的第一设备，以及包括存储器单元阵列的第二设备，执行控制流指令的执行单元，以及控制器，其被配置为控制控制流指令的执行 数据存储在数组中。

    MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES
    18.
    发明申请
    MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES 有权
    存储器控制器方法和系统补偿存储器单元数据丢失

    公开(公告)号：US20140181613A1

    公开(公告)日：2014-06-26

    申请号：US14189607

    申请日：2014-02-25

    Applicant: Micron Technology, Inc.

    Inventor： Dean A. Klein

    IPC: G11C11/406 ,  G11C29/08

    CPC classification number: G11C11/40611 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4072 ,  G11C29/08 ,  G11C2211/4062

    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

    Abstract translation: 计算机系统包括耦合到包含多个DRAM的存储器模块的存储器控​​制器。 存储器模块还包括存储行地址的非易失性存储器，其识别包含在存储器单元的正常刷新期间可能丢失数据的DRAM存储器单元的行。 上电时，来自非易失性存储器的数据被传送到存储器控制器中的比较器。 比较器将行地址与刷新影子计数器的行地址进行比较，该刷新阴影计数器标识要刷新的DRAM中的行。 当刷新一行存储单元位于距离可能会丢失数据的行的行的一半以上时，内存控制器会导致可能会松动数据的行被刷新。 存储器控制器还包括用于识别在刷新期间可能丢失数据的存储器单元的行的错误检查电路。

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