公开(公告)号：US10410696B2

公开(公告)日：2019-09-10

申请号：US15857597

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/30

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US20190272861A1

公开(公告)日：2019-09-05

申请号：US16416425

申请日：2019-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/22 ,  G06F9/30 ,  G11C7/10

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US20180089113A1

公开(公告)日：2018-03-29

申请号：US15280611

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20140077852A1

公开(公告)日：2014-03-20

申请号：US14083875

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Tyler J. Gomm ,  Debra Bell

IPC: H03L7/08

CPC classification number: H03L7/0802 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract translation: 提供了一种用于控制用于实现功率降低的延迟线的方法和装置。 该装置包括延迟锁定环路，以基于参考信号和反馈信号之间的相位差来提供输出信号，所述延迟锁定环路包括至少一个延迟电路，该延迟电路包括多个逻辑门，该多个逻辑门被配置为提供基本均匀的降级 处于静态的多个NAND门。

公开(公告)号：US20190087360A1

公开(公告)日：2019-03-21

申请号：US16192509

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B. Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US09892770B2

公开(公告)日：2018-02-13

申请号：US14693769

申请日：2015-04-22

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/30

CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.