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    APPARATUSES AND METHODS FOR SCALABLE MEMORY
    11.
    发明申请
    APPARATUSES AND METHODS FOR SCALABLE MEMORY 审中-公开

    公开(公告)号：US20190096855A1

    公开(公告)日：2019-03-28

    申请号：US16199460

    申请日：2018-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin ,  Yuanzhong Wan

    IPC: H01L25/065 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22

    Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.

    Output impedance calibration for signaling
    12.
    发明授权
    Output impedance calibration for signaling 有权

    公开(公告)号：US10128842B1

    公开(公告)日：2018-11-13

    申请号：US15934663

    申请日：2018-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin

    IPC: H03K19/0175 ,  H03K19/00 ,  G11C7/10 ,  G11C5/06 ,  G11C29/02 ,  H03K19/0185

    Abstract: Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.

    Flexible input/output transceiver
    13.
    发明授权
    Flexible input/output transceiver 有权
    灵活的输入/输出收发器

    公开(公告)号：US09287859B2

    公开(公告)日：2016-03-15

    申请号：US13866712

    申请日：2013-04-19

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin

    IPC: G11C8/00 ,  H03K5/003 ,  G11C7/10

    CPC classification number: H03K5/003 ,  G11C7/1057 ,  G11C7/1069 ,  G11C2207/107

    Abstract: An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit. The pre-driver circuit can modify a data signal in response to the feedback control signal and the data signal. A driver circuit is coupled to the pre-driver circuit and can provide a driver output signal responsive to the modified data signal. A receiver can be coupled to the driver to receive the driver output signal. The receiver includes a level shifting circuit that shifts the received signal to a voltage level determined by a selected signaling interface.

    Abstract translation: I / O收发器包括具有反馈电路的驱动器，该反馈电路具有模式选择信号输入，串行数据信号输入和驱动器输出信号输入。 反馈电路可以提供耦合到预驱动器电路的反馈控制信号。 预驱动器电路可以响应于反馈控制信号和数据信号来修改数据信号。 驱动器电路耦合到预驱动器电路，并且可以响应于修改的数据信号来提供驱动器输出信号。 接收器可以耦合到驱动器以接收驱动器输出信号。 接收机包括电平移位电路，该电平移位电路将接收到的信号转换到由所选信令接口确定的电压电平。

    Programmable channel equalization for multi-level signaling
    16.
    发明授权
    Programmable channel equalization for multi-level signaling 有权

    公开(公告)号：US11902060B2

    公开(公告)日：2024-02-13

    申请号：US17323967

    申请日：2021-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03885 ,  H04L25/0288 ,  H04L25/03343 ,  H04L2025/03363 ,  H04L2025/03433 ,  H04L2025/03777

    Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

    Apparatuses and methods for scalable memory
    18.
    发明授权
    Apparatuses and methods for scalable memory 有权

    公开(公告)号：US10325884B2

    公开(公告)日：2019-06-18

    申请号：US16199460

    申请日：2018-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin ,  Yuanzhong Wan

    IPC: G11C11/00 ,  G11C7/02 ,  H01L25/065 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/22

    Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.

    Apparatuses and methods for scalable memory
    19.
    发明授权
    Apparatuses and methods for scalable memory 有权

    公开(公告)号：US10153251B2

    公开(公告)日：2018-12-11

    申请号：US15174019

    申请日：2016-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Feng Lin ,  Yuanzhong Wan

    IPC: G11C11/00 ,  H01L25/065 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22

    Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.

    Analog delay lines and adaptive biasing
    20.
    发明授权
    Analog delay lines and adaptive biasing 有权
    模拟延迟线和自适应偏置

    公开(公告)号：US09203386B2

    公开(公告)日：2015-12-01

    申请号：US14322269

    申请日：2014-07-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Feng Lin

    IPC: H03H11/26 ,  H03K5/13

    CPC classification number: H03K5/133 ,  H03H11/26 ,  H03H11/265 ,  H03K5/131

    Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

    Abstract translation: 描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。 描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。 偏置信号可以部分地基于模拟延迟线的操作频率。

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