公开(公告)号：US20200336135A1

公开(公告)日：2020-10-22

申请号：US16920315

申请日：2020-07-02

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/10 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US20240046976A1

公开(公告)日：2024-02-08

申请号：US18225878

申请日：2023-07-25

Applicant: Micron Technology, Inc.

Inventor： Luigi Pilolli ,  Guan Wang ,  Rosario D’Esposito ,  Andrew Proescholdt ,  Lucia Botticchio ,  Luca Di Loreto

IPC: G11C11/4076 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4099 ,  G11C11/4096 ,  G11C2207/2254

Abstract: Operations include generating a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of a memory device, comparing the voltage level to a reference voltage level to generate a comparison result, generating based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and adjusting the duty cycle associated with digital signal based on the command.

公开(公告)号：US20220374370A1

公开(公告)日：2022-11-24

申请号：US17880226

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

IPC: G06F13/16 ,  H03K3/017 ,  G11C16/32

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

公开(公告)号：US20210218388A1

公开(公告)日：2021-07-15

申请号：US17214262

申请日：2021-03-26

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  H04L25/06 ,  G11C29/02 ,  H03K5/156 ,  H04L7/00 ,  H04L25/02

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US10727816B2

公开(公告)日：2020-07-28

申请号：US16204841

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US12073918B2

公开(公告)日：2024-08-27

申请号：US18097668

申请日：2023-01-17

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Luigi Pilolli

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03K3/356

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1087 ,  H03K3/356095

Abstract: A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.

公开(公告)号：US11768782B2

公开(公告)日：2023-09-26

申请号：US17880226

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

IPC: G06F13/16 ,  G11C16/32 ,  H03K3/017 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C7/22 ,  H03K5/156 ,  G11C16/04

CPC classification number: G06F13/1668 ,  G11C16/32 ,  H03K3/017 ,  G11C16/0483

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

公开(公告)号：US11079946B2

公开(公告)日：2021-08-03

申请号：US16171442

申请日：2018-10-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Guan Wang ,  Qiang Tang

IPC: G06F3/06 ,  G11C16/32

Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

公开(公告)号：US10270429B1

公开(公告)日：2019-04-23

申请号：US15848796

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  G11C7/22 ,  H03K5/156

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.