公开(公告)号：US20220413699A1

公开(公告)日：2022-12-29

申请号：US17362542

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ashutosh Malshe ,  Huachen Li ,  Giuseppe D'eliseo ,  Jianmin Huang

IPC: G06F3/06

Abstract: An apparatus can include a partial superblock memory management component. The partial superblock memory management component can identify bad blocks in respective planes of a block of non-volatile memory cells. The partial superblock memory management component can determine that a plane of the respective planes includes at least good block in at least one different block of non-volatile memory cells. The partial superblock memory management component can perform an operation to reallocate the at least one good block in the plane to the at least one bad block in the plane to form blocks of non-volatile memory cells having a quantity of bad blocks that satisfies a bad block threshold.

公开(公告)号：US20250004939A1

公开(公告)日：2025-01-02

申请号：US18546738

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Huachen Li

IPC: G06F12/02

Abstract: Methods, systems, and devices for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.

公开(公告)号：US11995337B2

公开(公告)日：2024-05-28

申请号：US17283210

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Zhou Zhou ,  Chaofeng Zhang ,  Jianfeng Li ,  Chen Huang ,  Lin Huang ,  Wei Li

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.

公开(公告)号：US11409462B2

公开(公告)日：2022-08-09

申请号：US16959064

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Zhong Xian Li ,  Xinghui Duan ,  Xing Wang ,  Tian Liang

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).