公开(公告)号：US20240296090A1

公开(公告)日：2024-09-05

申请号：US18415627

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20230231578A1

公开(公告)日：2023-07-20

申请号：US17894777

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Paolo AMATO

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/159 ,  H03M13/617

Abstract: There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

公开(公告)号：US20250013537A1

公开(公告)日：2025-01-09

申请号：US18678968

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN

IPC: G06F11/10

Abstract: A memory access method with improved bandwidth efficiency for reliability, availability, and serviceability (RAS) is described. The memory access method includes, in response to a memory access request, obtaining, using a first access granularity, a sub-stripe from a stripe of data stored on a plurality of memory media components arranged in a redundant array of independent data (RAID), and detecting an error in the sub-stripe of the data. The method further includes, in response to the detecting the error, obtaining, using a second access granularity, the stripe of the data from the plurality of memory media components, wherein the second access granularity is larger than the first access granularity. Corresponding devices are also described.

公开(公告)号：US20240345920A1

公开(公告)日：2024-10-17

申请号：US18415634

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1004

Abstract: Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.

公开(公告)号：US20240272981A1

公开(公告)日：2024-08-15

申请号：US18415632

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1068

Abstract: Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.

公开(公告)号：US20230236753A1

公开(公告)日：2023-07-27

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Angelo VISCONTI ,  Giorgio SERVALLI ,  Daniele BALLUCHI ,  Paolo AMATO

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.