公开(公告)号：US09779826B1

公开(公告)日：2017-10-03

申请号：US15657451

申请日：2017-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Mattia Cichocki ,  Tommaso Vali ,  Maria-Luisa Gallese ,  Umberto Siciliani

IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C8/06 ,  G11C8/12 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C8/06 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/32

Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.

公开(公告)号：US09754674B2

公开(公告)日：2017-09-05

申请号：US15288010

申请日：2016-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Mattia Cichocki ,  Tommaso Vali ,  Maria-Luisa Gallese ,  Umberto Siciliani

IPC: G11C11/34 ,  G11C16/26 ,  G11C8/06 ,  G11C8/12 ,  G11C11/56 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C8/06 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/32

Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.

公开(公告)号：US20150019787A1

公开(公告)日：2015-01-15

申请号：US14330076

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Luigi Pilolli ,  Maria-Luisa Gallese ,  Mauro Castelli

IPC: G06F13/40 ,  G06F12/06

CPC classification number: G06F13/4027 ,  G06F12/0607 ,  G06F2212/254 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract translation: 本公开包括与数据交织模块相关的装置和方法。 许多方法可以包括根据由装置支持的每个存储器单元的多个数据密度中选择的一个，在模块之间交换从总线接收的数据，并将交错的数据从模块传送到寄存器。