公开(公告)号：US09189440B2

公开(公告)日：2015-11-17

申请号：US14330076

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Luigi Pilolli ,  Maria-Luisa Gallese ,  Mauro Castelli

IPC: G11C7/10 ,  G06F13/40 ,  G06F12/06 ,  G11C11/56

CPC classification number: G06F13/4027 ,  G06F12/0607 ,  G06F2212/254 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract translation: 本公开包括与数据交织模块相关的装置和方法。 许多方法可以包括根据由装置支持的每个存储器单元的多个数据密度中选择的一个，在模块之间交换从总线接收的数据，并将交错的数据从模块传送到寄存器。

公开(公告)号：US09349423B2

公开(公告)日：2016-05-24

申请号：US14476323

申请日：2014-09-03

Applicant: Micron Technology, Inc.

Inventor： Mauro Castelli ,  Luca De Santis ,  Luigi Pilolli ,  Maria Luisa Gallese

IPC: G11C7/22 ,  G11C5/14

CPC classification number: G11C7/222 ,  G11C5/04 ,  G11C5/14 ,  G11C7/062 ,  G11C8/10

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

Abstract translation: 一些实施例包括具有耦合到多个存储器设备，存储器单元和模块以对存储器单元执行操作的节点的装置和方法，以使得在节点处的信号的电平的水平依次改变至少一个 以请求执行操作的特定阶段，使得该请求可由存储器件检测，并且在请求被确认之后执行操作的特定阶段。 描述其他实施例。

公开(公告)号：US20240086104A1

公开(公告)日：2024-03-14

申请号：US18243344

申请日：2023-09-07

Applicant: Micron Technology, Inc.

Inventor： Mauro Castelli ,  Luigi Pilolli

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0679

Abstract: Multiple copies of a stored data are sensed from a subset of memory cells of an array of memory cells into a plurality of latch elements in a page buffer coupled to the array of memory cells. Two or more latch elements are selected by enabling a respective select line of each of the two or more latch elements. An output data is determined based on a sensing of the conducting line driven by the two or more latch elements.

公开(公告)号：US10170167B2

公开(公告)日：2019-01-01

申请号：US15162128

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Mauro Castelli ,  Luca De Santis ,  Luigi Pilolli ,  Maria Luisa Gallese

IPC: G11C7/22 ,  G11C5/14 ,  G11C7/06 ,  G11C8/10 ,  G11C5/04

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

公开(公告)号：US20160267953A1

公开(公告)日：2016-09-15

申请号：US15162128

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Mauro Castelli ,  Luca De Santis ,  Luigi Pilolli ,  Maria Luisa Gallese

IPC: G11C7/22 ,  G11C8/10 ,  G11C7/06 ,  G11C5/14

CPC classification number: G11C7/222 ,  G11C5/04 ,  G11C5/14 ,  G11C7/062 ,  G11C8/10

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

公开(公告)号：US20160064052A1

公开(公告)日：2016-03-03

申请号：US14476323

申请日：2014-09-03

Applicant: Micron Technology, Inc.

Inventor： Mauro Castelli ,  Luca De Santis ,  Luigi Pilolli ,  Maria Luisa Gallese

IPC: G11C7/22 ,  G11C5/14

CPC classification number: G11C7/222 ,  G11C5/04 ,  G11C5/14 ,  G11C7/062 ,  G11C8/10

Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

Abstract translation: 一些实施例包括具有耦合到多个存储器设备，存储器单元和模块以对存储器单元执行操作的节点的装置和方法，以使得在节点处的信号的电平的水平依次改变至少一个 以请求执行操作的特定阶段，使得该请求可由存储器件检测，并且在请求被确认之后执行操作的特定阶段。 描述其他实施例。

公开(公告)号：US20150019787A1

公开(公告)日：2015-01-15

申请号：US14330076

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Luigi Pilolli ,  Maria-Luisa Gallese ,  Mauro Castelli

IPC: G06F13/40 ,  G06F12/06

CPC classification number: G06F13/4027 ,  G06F12/0607 ,  G06F2212/254 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract translation: 本公开包括与数据交织模块相关的装置和方法。 许多方法可以包括根据由装置支持的每个存储器单元的多个数据密度中选择的一个，在模块之间交换从总线接收的数据，并将交错的数据从模块传送到寄存器。