公开(公告)号：US20240086115A1

公开(公告)日：2024-03-14

申请号：US18513742

申请日：2023-11-20

Applicant: Micron Technology, Inc.

Inventor： Daniel J. Hubbard ,  Roy Leonard

IPC: G06F3/06 ,  G06F12/0846 ,  G06F12/0882

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0851 ,  G06F12/0882

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

公开(公告)号：US11887681B2

公开(公告)日：2024-01-30

申请号：US17675477

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Vamsi Rayaprolu ,  Ashutosh Malshe ,  Gary Besinga ,  Roy Leonard

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.

公开(公告)号：US20230297279A1

公开(公告)日：2023-09-21

申请号：US17698182

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0659 ,  G06F3/0635 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0811

Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.