APPARATUSES AND METHODS FOR ASYMMETRIC BI-DIRECTIONAL SIGNALING INCORPORATING MULTI-LEVEL ENCODING

    公开(公告)号:US20190384728A1

    公开(公告)日:2019-12-19

    申请号:US16553065

    申请日:2019-08-27

    Inventor: Timothy Hollis

    Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

    Reference Voltage Generation for Single-Ended Communication Channels
    12.
    发明申请
    Reference Voltage Generation for Single-Ended Communication Channels 有权
    单端通信信道的参考电压产生

    公开(公告)号:US20140049244A1

    公开(公告)日:2014-02-20

    申请号:US14059095

    申请日:2013-10-21

    CPC classification number: G05F3/08 H03K19/0175

    Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq.

    Abstract translation: 公开了一种改进的参考电压(Vref)发生器,可用于例如感​​测单端通道上的数据。 Vref发生器可以放置在包含接收器的集成电路上,或者可以放在芯片外。 在一个实施例中,Vref发生器包括与电流源组合的可调电阻分压器。 分压器参考I / O电源Vddq和Vssq,其中Vref在分压器的可调电阻之间的节点处产生。 电流源将电流注入到Vref节点中,并将其分成由分压器中使用的相同电阻器形成的不变的戴维南等效电阻。 所产生的电压等于两个项的和:包括Vref和Vddq之间的斜率的第一项,以及包括Vref偏移的第二项。 这些术语中的每一个可以在第一和第二模式中独立调整:通过分压器的斜率项,以及偏移项由注入电流的大小。 在一个有用的实现中使用所公开的Vref发生器允许在Vddq的两个不同值处优化Vref。

    APPARATUSES AND METHODS FOR ASYMMETRIC BI-DIRECTIONAL SIGNALING INCORPORATING MULTI-LEVEL ENCODING

    公开(公告)号:US20170132162A1

    公开(公告)日:2017-05-11

    申请号:US15412826

    申请日:2017-01-23

    Inventor: Timothy Hollis

    Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

    Systems and methods for lowering interconnect capacitance
    15.
    发明授权
    Systems and methods for lowering interconnect capacitance 有权
    降低互连电容的系统和方法

    公开(公告)号:US08994150B2

    公开(公告)日:2015-03-31

    申请号:US13674535

    申请日:2012-11-12

    Inventor: Timothy Hollis

    Abstract: Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

    Abstract translation: 公开了用于降低互连电容的方法和装置。 示例性设备可以包括形成在至少一个集成电路中并被配置为使信号通过至少一个集成电路的至少一部分的互连。 该装置可以包括在第一电压和第二电压下操作的发射器,并且向互连的端节点输出从第一电压到第三电压的减小的摆动信号。 第三电压可以在第一和第二电压之间,并且与在第二电压下操作发射机相比,减小的摆动信号可以操作以减小互连的电容。 公开了附加的装置和方法。

    Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System
    16.
    发明申请
    Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System 有权
    模拟计算机系统中信号的传输和同时切换输出噪声

    公开(公告)号:US20130317796A1

    公开(公告)日:2013-11-28

    申请号:US13959360

    申请日:2013-08-05

    Inventor: Timothy Hollis

    CPC classification number: G06F17/5009 G06F17/5036 G06F2217/10 G06F2217/82

    Abstract: Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation.

    Abstract translation: 公开了在用于模拟跨多个数据信道(总线)上的信号传输的计算机系统中可实现的方法。 所公开的技术通过产生每个的概率分布函数(PDF)来模拟符号间干扰(ISI),串扰和同时切换输出(SSO)噪声的影响。 所得到的PDF被卷积以得到指示接收每个这些非理想性的数据的总的PDF。 总的PDF及其基本术语可以索引到总线的特定通道以及特定的逻辑状态。 使用所公开的技术允许通过最少的计算和模拟来确定误码率和感测裕度。

    APPARATUSES AND METHODS FOR ASYMMETRIC BI-DIRECTIONAL SIGNALING INCORPORATING MULTI-LEVEL ENCODING

    公开(公告)号:US20220121585A1

    公开(公告)日:2022-04-21

    申请号:US17566127

    申请日:2021-12-30

    Inventor: Timothy Hollis

    Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

    Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
    19.
    发明授权
    Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding 有权
    包含多级编码的非对称双向信令的装置和方法

    公开(公告)号:US09577854B1

    公开(公告)日:2017-02-21

    申请号:US14831517

    申请日:2015-08-20

    Inventor: Timothy Hollis

    CPC classification number: G06F13/1689 G06F13/4068 H04L25/4917 H04L27/02

    Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

    Abstract translation: 公开了包含多级编码的非对称双向信令的装置和方法。 示例性装置可以包括第一和第二信道,耦合到第一和第二信道的接收机以及分别耦合到第一和第二信道的第一和第二发射机。 接收机可以被配置为接收差分数据信号以以一定的速率接收写入数据,并且第一和第二发射机中的每一个可以被配置为将多个比特编码成相应的数据信号,并以数据速率提供相应的数据信号 。

    Reference Voltage Generator for Single-Ended Communication Systems
    20.
    发明申请
    Reference Voltage Generator for Single-Ended Communication Systems 有权
    单端通信系统参考电压发生器

    公开(公告)号:US20140044220A1

    公开(公告)日:2014-02-13

    申请号:US14053200

    申请日:2013-10-14

    Inventor: Timothy Hollis

    Abstract: An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system.

    Abstract translation: 公开了用于通信系统中的单端接收机的改进的参考电压(Vref)发生器。 一个示例中的Vref发生器包括用于向电阻器Rb提供电流I以产生Vref电压(I * Rb)的级联电流源。 因为电流源将Vref与两个电源中的第一个隔离,所以Vref将仅随耦合到Rb的第二个电源而变化。 因此,改进的Vref发生器在使用参考该第二电源但具有解耦第一电源的信令的系统中是有用的。 例如,在其中第二电源(例如Vssq)对于两个装置是公共的但是第一电源(Vddq)不是)的通信系统中,所公开的Vref发生器产生用于跟踪Vssq而不是第一电源的Vref的值。 这改善了在这种系统中对Vssq参考信号的感测。

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