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    PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    15.
    发明申请
    PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权

    公开(公告)号：US20240403160A1

    公开(公告)日：2024-12-05

    申请号：US18800272

    申请日：2024-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

    IPC: G06F11/10 ,  G11C11/00 ,  G11C11/4074 ,  G11C11/4096

    Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

    PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    16.
    发明公开
    PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM) 审中-公开

    公开(公告)号：US20230185660A1

    公开(公告)日：2023-06-15

    申请号：US18108876

    申请日：2023-02-13

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

    IPC: G06F11/10 ,  G11C11/00

    CPC classification number: G06F11/1004 ,  G06F11/1068 ,  G11C11/005 ,  G11C11/4096

    Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

    Separate partition for buffer and snapshot memory
    17.
    发明授权
    Separate partition for buffer and snapshot memory 有权

    公开(公告)号：US11385819B2

    公开(公告)日：2022-07-12

    申请号：US16995682

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

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